This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON gate insulators in order to keep up with Moore's scaling law. The issue is still relevant and also very much exits in the recently introduced HKMG gate stacks.

In part 3, the final part, I will discuss NBTI physical mechanism, and build a simple model to explain measured data obtained from a wide variety of devices during DC stress, recovery following DC stress and during AC stress as a function of frequency and duty cycle. A predictive model for lifetime determination under use condition will also be discussed.

Researchers should cite this work as follows:

• Souvik Mahapatra (2012), "Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Predictive Modeling (Part 3 of 3) ," https://nanohub.org/resources/13612.

  BibTex | EndNote

1. CMOS
2. CMOS device reliability
3. Device Characterization
4. device modelling and simulation
5. MOSFET
6. MOSFET modeling
7. nanoelectronics
8. Negative Bias Temperature Instability
9. reliability