JFETIDG Model for Independent Dual-Gate JFETs 1.0.3

By Colin McAndrew1, Kejun Xia1

NXP Semiconductors

JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.

Listed in Compact Models

Additional materials available

Version 1.0.3 - published on 27 Jul 2017 doi:10.4231/D3KK94F1N - cite this

Licensed under NEEDS Modified CMC License according to these terms

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Versions

Version Released DOI Handle Status
1.0.3 Jul 19, 2017 10.4231/D3KK94F1N published view version »
1.0.0 Mar 24, 2017 10.4231/D3TD9N91H published view version »