This is the Verilog-A model of the magnetic tunnel junction developed by the Nanoelectronics Research Laboratory at Purdue University.

• Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0 Verilog-A(VA | 7 KB)
• Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0 Benchmarks(ZIP | 300 KB)
• Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0 Parameters(SP | 810 B )
• Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0 Manual(PDF | 360 KB)
• Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0 Parameter Extractor(ZIP | 5 KB)
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[1] D. Datta, B. Behin-Aein, S. Datta, and S. Salahuddin, "Voltage asymmetry of spin-transfer torques," IEEE Trans. Nanotechnology, vol. 11, no. 2, pp. 261–272, Mar. 2012.

[2] G. Panagopoulos, C. Augustine, and K. Roy, "A framework for simulating hybrid MTJ/CMOS circuits: atoms to systems approach," in Proc. of IEEE Design and Test in Europe (DATE), Apr. 2012, pp. 1443–1446.

[3] X. Fong et al., "KNACK: a hybrid spin-charge mixed-mode simulator for evaluating different genres of STT-MRAMs," in Proc. of IEEE Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 2011, pp. 51–54.

[4] [Online] OOMMF. Available: "http://math.nist.gov/oommf".

[5] S. Yuasa et al., "Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions," Nature Materials, vol. 3, iss. 12, pp. 868–871, Dec. 2004.

[6] C. J. Lin et al., "45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell," in Proc. of IEEE Int. Electron Devices Meeting (IEDM), Dec. 2009, pp. 11.6.1–11.6.4.

Researchers should cite this work as follows:

• Fong, X.; Choday, S. H.; Georgios, P.; Augustine, C.; Roy, K. (2014). Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model. nanoHUB. doi:10.4231/D33R0PV04

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1. Compact Model
2. NEEDS node