JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Verilog-A
general_v1_0_1.va26 KB- jfetidg_v1_0_3.va73 KB
- jfetidgIds_v1_0_1.va20 KB
- junction_v1_0_1.va19 KB
- simulatorFlags.va688 B
Benchmarks- qaJfetidg73 KB
- qaJfetidgTemp4 KB
- reference.tar.gz707 KB
- Parameters
- parameterSets522 B
- Manual
- doc.tar.gz170 KB
Miscellaneous/2016TED_JFETIDGpartI.pdf2 MB- Miscellaneous/2016TED_JFETIDGpartII.pdf3 MB
Miscellaneous/_00_README.txt4 KB
gallery/crossSection.png13 KB- gallery/equivalentCircuit.png15 KB
- LICENSE.txt
- hubREADME.txt