JFETIDG Model for Independent Dual-Gate JFETs 1.0.3
JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.
Listed in Compact Models
Additional materials available
Version 1.0.3 - published on 27 Jul 2017 doi:10.4231/D3KK94F1N - cite this
Licensed under NEEDS Modified CMC License according to these terms
Supporting Docs
- JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Verilog-A(ZIP | 31 KB)
- JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Benchmarks(ZIP | 664 KB)
- JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Parameters(VAR/WWW/NANOHUB/APP/SITE/PUBLICATIONS/00173/00218/4Y05EKEAJY/PARAMETERS/PARAMETERSETS | 522 B )
- JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Manual(GZ | 170 KB)
- 2016TED_JFETIDGpartI.pdf(PDF | 2 MB)
- 2016TED_JFETIDGpartII.pdf(PDF | 3 MB)
- _00_README.txt(TXT | 4 KB)