The MIT virtual source (MVS) nanotransistor model provides a simple, physical description of transistors that operate in the quasi-ballistic regime. With only a few empirical parameters that are easily obtained through device characterization, the MVS model has served well for technology benchmarking and more recently it was extended to a full-fledged compact model and validated via circuit simulation and comparison with experimental data on both silicon and III-V transistors.

In this talk, I will present my view on building an industry-standard compact model by using the MVS model as a case study. In the first part of the talk, I discuss mathematical issues, such as the smoothness of functions and their higher-order derivatives in connection with the MVS model. While mathematical smoothing techniques are commonly used in compact models to ensure convergence of circuit simulation, they may also produce undesirable and misleading artifacts in simulation. Examples from the MVS model will be used to highlight the merits and limitations of commonly used mathematical smoothing techniques. I will also introduce the definition and testing methodology for MOSFET symmetry and discuss the response of the MVS model to the various symmetry operations.

The performance of a Verilog-A model depends on being aware of and avoiding the use of performance-inhibiting constructs present in the language. In the second part of the talk, I will discuss “language constructs to avoid” in writing Verilog-A code by showing specific examples from the MVS Verilog-A implementation. Resolving some of the issues present in our current MVS model implementation has proven to be challenging. My goal for this talk is to start an open discussion about compact models and their implementation issues. Audience feedback is strongly encouraged.