9nm GaSb-InAs TFET Models with Doped Source Underlap for Circuit Simulations
03 Dec 2014 | Contributor(s): Ankit Sharma, Arun Goud Akkala, Kaushik Roy
This zip contains Verilog-A compact lookup table models for 9nm channel length GaSb-InAs TFET which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic tight binding transport simulator (also...
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic...
Brillouin Zone Viewer
Tools | 25 Jan 2011 | Contributor(s): Prasad Sarangapani, Arun Goud Akkala, Sebastian Steiger, Hong-Hyun Park, Yosef Borga, Tillmann Christoph Kubis, Michael Povolotskyi, Gerhard Klimeck
Visualize Brillouin zones of different crystals and different unit cells
Resonant Tunneling Diode Simulation with NEGF
Tools | 18 Aug 2008 | Contributor(s): Hong-Hyun Park, Zhengping Jiang, Arun Goud Akkala, Sebastian Steiger, Michael Povolotskyi, Tillmann Christoph Kubis, Jean Michel D Sellier, Yaohua Tan, SungGeun Kim, Mathieu Luisier, Samarth Agarwal, Michael McLennan, Gerhard Klimeck, Junzhe Geng
Simulate 1D RTDs using NEGF.
1D Heterostructure Tool
Tools | 04 Aug 2008 | Contributor(s): Arun Goud Akkala, Sebastian Steiger, Jean Michel D Sellier, Sunhee Lee, Michael Povolotskyi, Tillmann Christoph Kubis, Hong-Hyun Park, Samarth Agarwal, Gerhard Klimeck, James Fonseca, Archana Tankasala, Kuang-Chung Wang, Chin-Yi Chen, Fan Chen
Poisson-Schrödinger Solver for 1D Heterostructures
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