9nm GaSb-InAs TFET Models with Doped Source Underlap for Circuit Simulations

By Ankit Sharma1; Arun Goud Akkala1; Kaushik Roy1

1. Purdue University

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Abstract

This zip contains Verilog-A compact lookup table models for 9nm channel length GaSb-InAs TFET which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic tight binding transport simulator (also available on Nanohub.org).
Usage notes, example input netlists and full device description are also included.

Credits

We wish to thank the NEMO5 team for granting us access to the NEMO5 simulator and for providing technical support. This work was funded under the DARPA PERFECT program.

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DARPA

References

Tillmann Christoph Kubis; Michael Povolotskyi; Jean Michel D Sellier; James Fonseca; Gerhard Klimeck (2012), "NEMO5 Overview Presentation," https://nanohub.org/resources/14701. HSPICE - http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx Verilog-A - http://www.accellera.org/downloads/standards/v-ams/VAMS-LRM-2-3-1.pdf

Publications

A. Sharma, A. A . Goud, K. Roy, "GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths", IEEE Electron Device Letters, pp.1221-1223, Dec 2014.

Cite this work

Researchers should cite this work as follows:

  • Ankit Sharma, Arun Goud Akkala, Kaushik Roy (2014), "9nm GaSb-InAs TFET Models with Doped Source Underlap for Circuit Simulations," https://nanohub.org/resources/21737.

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