Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization
Online Presentations | 04 Oct 2017 | Contributor(s): Chi-Shuen Lee, Saurabh Vinayak Suryavanshi, H.-S. Philip Wong
RRAM Models and Applications to Circuits and Systems
Online Presentations | 08 Sep 2017 | Contributor(s): Haitong Li, Zizhen Jiang, H.-S. Philip Wong
Schottky-Barrier CNFET
Tools | 16 Mar 2007 | Contributor(s): Arash Hazeghi, Tejas Krishnamohan, H.-S. Philip Wong
Simulate Carbon Nanotube field Effect transistor with Schottky Barriers
Resonant Tunneling Diodes: an Exercise
4.0 out of 5 stars
Teaching Materials | 06 Jan 2006 | Contributor(s): H.-S. Philip Wong
This homework assignment was created by H.-S. Philip Wong for EE 218 "Introduction to Nanoelectronics and Nanotechnology" (Stanford University). It includes a couple of simple "warm up" exercises and two design problems, intended to teach students the electronic properties...
Top 4 shown
Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model
08 Apr 2015 | Contributor(s): Chi-Shuen Lee, H.-S. Philip Wong | doi:10.4231/D3BK16Q68
The VSCNFET model captures the dimensional scaling properties and includes parasitic resistance, capacitance, and tunneling leakage currents. The model aims for CNFET technology assessment for the sub-10-nm technology nodes.
30 Mar 2015 | Contributor(s): Chi-Shuen Lee, H.-S. Philip Wong | doi:10.4231/D38W3835S
Top 2 shown