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Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization

By Chi-Shuen Lee¹; Saurabh Vinayak Suryavanshi¹; H.-S. Philip Wong¹

1. Stanford University, Stanford, CA

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Additional materials available (4)

Category

Online Presentations

Published on

04 Oct 2017

Sponsored by

NEDS: Nano-Engineered Device Simulation Node

Cite this work

Researchers should cite this work as follows:

Chi-Shuen Lee, Saurabh Vinayak Suryavanshi, H.-S. Philip Wong (2017), "Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization," https://nanohub.org/resources/27371.

BibTex | EndNote

Time

11:00 am, 21 Jun 2017

Location

Room 101X, Paul G. Allen Building, Stanford University, Stanford, CA