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  1. Negative Capacitance Ferroelectric Transistors: A Promising Steep Slope Device Candidate?

    Online Presentations | 30 Oct 2015 | Contributor(s):: Suman Datta

    In this talk, we will review progress in non-perovskite ALD based ferroelectric dielectrics which have strong implication for VLSI compatible negative capacitance Ferroelectric FETs.

  2. Device Options and Trade-offs for 5 nm CMOS Technology Seminar Series

    Series | 05 Oct 2015 | Contributor(s):: Mark Lundstrom

    Today's CMOS technology is so-called 14-nm technology.  10 nm technology development is well underway, and 7 nm has begun. It will soon be time to select a technology for the 5 nm node. To help understand the device options, what each on promises, what the challenges and trade-offs are,...

  3. Nanometer-Scale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs

    Online Presentations | 05 Oct 2015 | Contributor(s):: Juses A. del Alamo

    This talk will review recent progress as well as challenges confronting III-V electronics for future logic applications with emphasis on the presenter’s research activities at MIT.

  4. Ivan C R nascimento

    https://nanohub.org/members/121504

  5. Design and Compact Modeling of CMOS-MEMS Resonant Body Transistors

    Online Presentations | 10 Jun 2014 | Contributor(s):: Dana Weinstein, Luca Daniel, Bichoy W. Bahr

    This talk presents the latest results of the CMOS Resonant Body Transistor (RBT) fabricated in standard 32nm SOI CMOS. Using phononic crystals formed from the CMOS stack, we will discuss methods for 10x improvement of Q and suppression of spurious modes.

  6. RF Solid-State Vibrating Transistors

    Online Presentations | 15 Feb 2014 | Contributor(s):: Dana Weinstein

    In this talk, I will discuss the Resonant Body Transistor (RBT), which can be integrated into a standard CMOS process. The first hybrid RF MEMS-CMOS resonators in Si at the transistor level of IBM’s SOI CMOS process, without any post-processing or packaging will be described. ...

  7. Computational and Experimental Study of Transport in Advanced Silicon Devices

    Papers | 28 Jun 2013 | Contributor(s):: Farzin Assad

    In this thesis, we study electron transport in advanced silicon devices by focusing on the two most important classes of devices: the bipolar junction transistor (BJT) and the MOSFET. In regards to the BJT, we will compare and assess the solutions of a physically detailed microscopic model to...

  8. Course on Beyond CMOS Computing

    Teaching Materials | 06 Jun 2013 | Contributor(s):: Dmitri Nikonov

    Complementary metal-oxide-semiconductor (CMOS) field effect transistors (FET) underpinned the development of electronics and information technology for the last 30 years. In an amazing saga of development, the semiconductor industry (with a leading role of Intel) has shrunk the size of these...

  9. Carbon-Based Nanoswitch Logic

    Online Presentations | 28 Mar 2013 | Contributor(s):: Stephen A. Campbell

    This talk discusses a rather surprising possibility: the use of carbon-based materials such as carbon nanotubes and grapheneto make nanomechanical switches with at least an order of magnitude lower power dissipation than the low power CMOS options and performance between the various CMOS...

  10. Mohamed Tarek Ghoneim

    Keywords: device physics, flexible electronics, nanotechnology, graphene, nonvolatile memory, reliability, CMOS, physical and electrical characterization, emerging devices, power management, VLSI,...

    https://nanohub.org/members/77955

  11. Selim Guncer

    Selim Guncer is an analog electronics specialist. After Ph.D. studies at Arizona State University with Prof. David K. Ferry in 1993 on semiconductor/quantum transport physics, he was with the...

    https://nanohub.org/members/77507

  12. Uniform Methodology of Benchmarking Beyond-CMOS Devices

    Online Presentations | 31 Oct 2012 | Contributor(s):: Dmitri Nikonov

    Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described.Theories used for benchmarking these devices are...

  13. Swapnil Christian

    Working as a Design Engineer with Boeing - Defense, space and security. Interested in exploring modern semiconductor devices

    https://nanohub.org/members/70861

  14. Krishnakali Chaudhuri

    https://nanohub.org/members/70104

  15. In Search of a Better MEMS-Switch: An Elementary theory of how nanostructured dielectrics may soften landing, increase travel range, and decrease energy dissipation

    Online Presentations | 06 Jun 2012 | Contributor(s):: Muhammad Alam

    In this talk, I will discuss an elementary theory of the role of nanostructured electrodes in addressing some of the challenges from a fundamentally different perspective. The goal is to start a conversation regarding the viability of the approaches suggested and see if the perspective offered is...

  16. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling

    Courses | 28 Mar 2012 | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...

  17. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Fast and Ultra-fast Characterization Methods (Part 1 of 3)

    Online Presentations | 28 Mar 2012 | Contributor(s):: Souvik Mahapatra

  18. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Predictive Modeling (Part 3 of 3)

    Online Presentations | 28 Mar 2012 | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...

  19. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: The Impact of Gate Insulator Processes (Part 2 of 3)

    Online Presentations | 28 Mar 2012 | Contributor(s):: Souvik Mahapatra

    This presentation is part 2 on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner...

  20. Eric Sanchez

    https://nanohub.org/members/63217