As Si electronics faces mounting difficulties to maintain its historical scaling path, transistors based on III-V compound semiconductors have emerged as a credible alternative. Fundamental technical problems had to be solved, but there are still many challenges that need to be addressed before the first non-Si CMOS technology becomes a reality. Among them, harnessing the outstanding electron transport properties of InGaAs, the leading n-channel material candidate for high-performance nanoscale MOSFET has proven difficult: contact resistance, off-state characteristics, reliability and Si integration remain serious problems. Introducing a new material system is not the only challenge, scalability to sub-10 nm gate dimensions also demands a new 3D transistor geometry. InGaAs FinFETs, Trigate MOSFETs and Nanowire MOSFETs have all been demonstrated but their performance is still disappointing. To compound the challenge, a high-performance nanoscale p-type transistor is also required. Among III-Vs, InGaSb is the most promising candidate. Planar MOSFETs have been demonstrated but more advanced geometries remain elusive. This talk will review recent progress as well as challenges confronting III-V electronics for future logic applications with emphasis on the presenter’s research activities at MIT.

Jesús A. del Alamo is the Director of the Microsystems Technology Laboratories at Massachusetts Institute of Technology. He obtained a Telecommunications Engineer degree from the Polytechnic University of Madrid and MS and PhD degrees in Electrical Engineering from Stanford University. From 1985 to 1988 he was with NTT LSI Laboratories in Atsugi (Japan) and since 1988 he has been with the Department of Electrical Engineering and Computer Science of MIT where he currently is the Donner Professor. His current research interests are centered on nanoelectronics based on compound semiconductors for future logic, communications and power management applications. Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the IEEE and the APS. He has received the Intel Outstanding Researcher Award, the SRC Technical Excellence Award, and the IEEE EDS Education Award.

NEEDS: Nano-Engineered Electronic Device Simulation Node, Network for Computational Nanotechnology, Discovery Park

Researchers should cite this work as follows:

• Juses A. del Alamo (2015), "Nanometer-Scale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs," https://nanohub.org/resources/22880.

  BibTex | EndNote

1. CMOS
2. III-V materials/devices
3. nanoelectronics
4. nanowires