Day 4 Session 1.2

Introduction: Resistive Random-Access Memory (ReRAM) devices with filamentary and non-filamentary resistive switching (RS) mechanisms are extensively explored for Neuromorphic applications to cater to the present-day dataintensive computing requirements. In filamentary RRAMs, the electric field and Joule heating dependent threshold switching is well established (Fig.1a) [1]. Alternatively, electric-field driven ionic transport was responsible for nonfilamentary memory characteristics (Fig.1b) [2]. In recent studies, self-heating-based mechanism in addition to ionic transport has been suggested in non-filamentary devices (Fig.1c) [3]. This boosts thermally activated ionic drift, thereby enhancing the switching behavior within the device. Different techniques like the incorporation of heater elements or thermally insulating layers such as GST to improve heat confinement within the stack has been proposed to improve device characteristics [4]. Recently, highly non-linear I-V characteristics have been demonstrated in PMO based RRAM in its Low Resistance State (LRS). The PMO material has very low thermal conductivity (0.5W/m-K), which facilitates thermal feedback leading to non-linearity (NL). Further, independent of enhanced RS, two capabilities of PMO-RRAM devices have been demonstrated. Firstly, NL enabled selector-less memory operations, which are highly attractive in crossbar memory arrays (Fig.1d) [5]. Secondly, it facilitates oscillations based on NL related NDR from thermal runaway(Fig.1e) [6,7]. Thus, investigating & engineering the NL is of significant interest. In this paper, we modify the thermal circuit of the PMO RRAM device stack by changing isolation SiO₂ thickness, keeping the rest of the electronic/ionic aspects of the RRAM structure identical. We show~ 38% reduction in threshold voltage in DC and an 8x improvement in heating transients as a response to thermal circuit engineering.

Device Fabrication: The devices with (10 μm x 10 μm) device area are being used for the study with Si/SiO₂/Ta/Pt/PMO/W structure (Fig.2a). Three stacks with different SiO₂ thicknesses (18 nm,87 nm, and 900 nm) are fabricated. SiO₂ layer provides not only mechanical strength to device stack, but also provides good thermal insulation due to its low thermal conductivity (1.1-1.4 W/m-K).

Characterization and Results: The hysteretic DC -IV switching characteristics of PMO based RRAM device is due to intrinsic Joule heating (Fig.2b). The input voltage of -2V with 10mA compliance is applied between two electrodes, and the current is measured for three devices with different SiO₂ thicknesses. The significant scaling in threshold voltage (VH) can be seen in Fig.2c. This is further validated with C2C (Fig.2d) and D2D (Fig.2e) variability, which shows a ~ 38% reduction in VH with a 100x increase in SiO₂ thickness. Following the DC-IV measurements, transient measurements are done with the current threshold of 10mA and pulse voltages (-1V to -2V). The transient characteristics for 1.65V voltage pulse are shown (Fig.3a, b). The sharp shoot-up(heating) timescales and shootdown( cooling) timescales are extracted from transient measurements (Fig.5). Transient measurement shows, at lower voltages, SiO₂-18nm doesn’t switch, whereas the SiO₂-900nm exhibits an 8x improvement in heating timescales over SiO₂-87nm (Fig.4a). In contrast, cooling timescales follow the opposite trend (Fig.4b). For oscillator applications, the aggregate of the two timescales is important. For lower voltages, the heating timescale dominates and provides an improvement in voltage as well as time; however, at higher voltages, the cooling timescales start dominating, and lower SiO₂ thickness gives better timescales (Fig.4c). From aggregate timescales, for a given frequency of say 1 MHz, voltage reduction of ~ 23% could be achieved, leading to ~ 50% power reduction (Table1).

Validation Through Thermal Modelling: The device structure was simulated in MATLAB PDE. The thermal resistance (RTH) of the device and the power density (current density x voltage) determines the device temperature. Therefore, for a given power density, the effect of increasing RTH is demonstrated through simulated temperature profiles (Fig.5a-c). Further, the extracted steady-state peak temperatures for three device stacks increase with the increase in SiO₂ thickness (Fig.5d) to qualitatively validate the enhanced thermal insulation with SiO₂ thickness.

Conclusion: Voltage Scaling through thermal engineering is significant from the power efficiency. Further, the speed scaling is important to inform selector-less applications and oscillations. This study is the first-time analysis of heating and cooling timescales together demonstrating voltage as well as frequency scaling for different voltage regimes w.r.t. different device stacks. Thus, an electro-thermal speed engineering study is critical for RRAM devices to model elements of neural networks that use NL characteristics.

The work is partially funded by DST, Nano Mission, and MeitY, India.S. Lashkare is supported jointly by the Visvesvaraya Ph.D. Scheme of MeitY, Government of India, and Intel Ph.D.

78^th Device Research Conference

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Researchers should cite this work as follows:

• Jayatika Sakhuja, Sandip Lashkare, Vivek Saraswat, Udayan Ganguly (2020), "39 Thermal Engineering of Volatile Switching in PrMnO3 RRAM: Non-Linearity in DC IV Characteristics and Transient Switching Speed," https://nanohub.org/resources/34110.

  BibTex | EndNote

1. devices
2. memory devices
3. nanoelectronics
4. Resistive Random-Access Memory (ReRAM)