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New Dimension in Performance: Harnessing 3D Integration Technology
Online Presentations | 29 Nov 2007 | Contributor(s):: Kerry Bernstein
Despite generation on generation of scaling, computer chips have remained essentially 2-dimensional. Improvements in on-chip wire delay, and in the total number of inputs and outputs has not been able to keep up with improvements to the transistor, and its getting harder and harder to hide it! 3D...
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Introduction to nanoMOS
Series | 02 Jul 2007 | Contributor(s):: James K Fodor, Jing Guo
This learning module introduces nanoHUB users to the nanoMOS simulator. A brief introduction to nanoMOS is presented, followed by voiced presentations featuring the simulator in action. Upon completion of this module, users should be able to use this simulator to gain valuable insight into the...
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Illinois Tools: MOCA
Tools | 28 Mar 2007 | Contributor(s):: Mohamed Mohamed, Umberto Ravaioli, Nahil Sobh, derrick kearney, Kyeong-hyun Park
2D Full-band Monte Carlo (MOCA) Simulation for SOI-Based Device Structures
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CGTB
Tools | 15 Jun 2006 | Contributor(s):: Gang Li, yang xu, Narayan Aluru
Compute the charge density distribution and potential variation inside a MOS structure by using a coarse-grained tight binding model
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NanoMOS
Tools | 19 May 2006 | Contributor(s):: , Sebastien Goasguen, Akira Matsudaira, Shaikh S. Ahmed, Kurtis Cantley, Yang Liu, Yunfei Gao, Xufeng Wang, Mark Lundstrom
2-D simulator for thin body (less than 5 nm), fully depleted, double-gated n-MOSFETs
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MOSCap
Tools | 06 Apr 2006 | Contributor(s):: Akira Matsudaira, Saumitra Raj Mehrotra, Shaikh S. Ahmed, Gerhard Klimeck, Dragica Vasileska
Capacitance of a MOS device
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Modeling Single and Dual-Gate Capacitors using SCHRED
Series | 31 Mar 2006 | Contributor(s):: Dragica Vasileska
SCHRED stands for self-consistent solver of the 1D Poisson and 1D effective mass Schrodinger equation as applied to modeling single gate or dual-gate capacitors. The program incorporates many features such as choice of degenerate and non-degenerate statistics for semiclassical charge description,...
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Schred
Tools | 30 Mar 2006 | Contributor(s):: Dragica Vasileska, Shaikh S. Ahmed, Gokula Kannan, Matteo Mannino, Gerhard Klimeck, Mark Lundstrom, Akira Matsudaira, Junzhe Geng
SCHRED simulation software calculates the envelope wavefunctions and the corresponding bound-state energies in a typical MOS, SOS and a typical SOI structure.
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New Frontiers in Nanocomputing
Series | 03 Nov 2005
Welcome to Frontiers in Nanocomputing, a seminar series that focuseson systems issues for nanoelectronics. Our topic was FundamentalLimits of Digital Computation. The questions to each speaker were: Whatare the fundamental limits? How close are we to those limits? Howrelevant are they...
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CMOS Nanotechnology
Online Presentations | 07 Jul 2004 | Contributor(s):: Mark Lundstrom
In non-specialist language, this talk introduces CMOS technology used for modern electronics. Beginning with an explanation of "CMOS," the speaker relates basic system considerations of transistor design and identifies future challenges for CMOS electronics. Anyone with an elementary...
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Schred Source Code Download
Downloads | 09 Mar 2005 | Contributor(s):: Dragica Vasileska, Zhibin Ren
Schred 2.0 calculates the envelope wavefunctions and the corresponding bound-state energies in a typical MOS (Metal-Oxide-Semiconductor) or SOS (Semiconductor-Oxide- Semiconductor) structure and a typical SOI structure by solving self-consistently the one-dimensional (1D) Poisson equation and the...
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Digital Electronics: Fundamental Limits and Future Prospects
Online Presentations | 20 Jan 2004 | Contributor(s):: Konstantin K. Likharev
I will review some old and some recent work on the fundamental (and not so fundamental) limits imposed by physics of electron devices on their density and power consumption.
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Nanoelectronic Scaling Tradeoffs: What does Physics Have to Say?
Presentation Materials | 23 Sep 2003 | Contributor(s):: Victor Zhirnov
Beyond CMOS, several completely new approaches to information-processing and data-storage technologies and architectures are emerging to address the timeframe beyond the current SIA International Technology Roadmap for Semiconductors (ITRS). A wide range of new ideas have been proposed for...