All Categories (1-4 of 4)

1. 

   Md. Sajjad Alam

   Hi I am Sajjad Alam. I am an Engineering student. I am studying B.Sc. in EEE in East West University, Dhaka, Bangladesh.

   https://nanohub.org/members/194989

2. JFETIDG Model for Independent Dual-Gate JFETs

   19 Jul 2017 | Compact Models | Contributor(s):

   By Colin McAndrew¹, Kejun Xia¹

   NXP Semiconductors

   JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical...

   https://nanohub.org/publications/173/?v=2

3. 

   Nikolaos Makris

   https://nanohub.org/members/160697

4. What can be flat band voltage for a double gate junction less device for p+ poly gate doped at 2 X 10^-14/cm2 and n-type silicon doped at 10^20/cm2?

   Q&A|Closed | Responses: 0

   https://nanohub.org/answers/question/1808