Compact Solver for Double-Gate Tunnel-FETs

Plotting of DC and AC characteristics of DG-Tunnel-FETs using equations of the corresponding Verilog-A compact model THM-TFET.

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Version 1.1 - published on 19 Apr 2021

doi:10.21981/EWV2-4V56 cite this

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Usage

World usage

Location of all "Compact Solver for Double-Gate Tunnel-FETs" Users Since Its Posting

Cumulative Simulation Users

157

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Simulation Runs

1,728

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Overview
Average Total
Wall Clock Time 2.71 hours 319.54 days
CPU time 4.28 seconds 3.37 hours
Interaction Time 14.35 minutes 28.22 days