Compact Solver for Double-Gate Tunnel-FETs

Plotting of DC and AC characteristics of DG-Tunnel-FETs using equations of the corresponding Verilog-A compact model THM-TFET.

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Version 1.1 - published on 19 Apr 2021

doi:10.21981/EWV2-4V56 cite this

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Abstract

This tool allows plotting of DC and AC characteristics of a double-gate Tunnel-FET using the equations of the corresponding Verilog-A compact model THM-TFET. The compact model allows the user to simulate circuits with Tunnel-FETs in DC, AC or transient mode using a conventional circuit simulator. This tool supports the use of the compact model, allows a rapid simulation of the characteristics of single Tunnel-FET devices, and gives deeper insight to the device physics. 

The tool and the corresponding Verilog-A compact model THM-TFET was developed by Device Modeling Research Group of NanoP, THM University of Applied Sciences, Germany.

The Verilog-A compact model THM-TFET is available on nanohub [5].

 

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Credits

Michael Graef, developer of the fundamental analytical modeling approach, which the compact model is based upon.

Sponsored by

Project funding: German Federal Ministry of Education and Research (BMBF), project no. FKZ 13FH010IX5

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Cite this work

Researchers should cite this work as follows:

  • Alexander Kloes, Fabian Horst, Anita Farokhnejad (2021), "Compact Solver for Double-Gate Tunnel-FETs," https://nanohub.org/resources/ctfet. (DOI: 10.21981/EWV2-4V56).

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