All Categories (41-51 of 51)

1. 

   Abdurrahman Javid Shaikh

   I am currently working towards my PhD at Collaborative µElectronic Design Excellence Centre (CEDEC), University Sains Malaysia (USM). My areas of interests include Theoretical and Computational...

   https://nanohub.org/members/55165

2. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling (2011)

   Online Presentations | 11 May 2011 | Contributor(s):: Souvik Mahapatra

   This is a presentation on Negative Bias Temperature Instability, or in short NBTI, observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to...

3. NanoV: Nanowire-based VLSI Design

   Downloads | 08 Sep 2010 | Contributor(s):: muzaffer simsir

   In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design...

4. 

   Akash Paharia

   Currently, I am an undergraduate student in Electrical Department of Indian Institute of Technology ,Delhi. I am interested in knowing about new technologies in the field of semiconductors device...

   https://nanohub.org/members/38550

5. ECE 612 Lecture 23: RF CMOS

   0.0 out of 5 stars 

   Online Presentations | 02 Dec 2008 | Contributor(s):: Mark Lundstrom

   Outline: 1) Introduction,2) Small signal model,3) Transconductance,4) Self-gain,5) Gain bandwidth product,6) Unity power gain,7) Noise, mismatch, linearity…,8) Examples

6. ECE 612 Lecture 22: CMOS Circuit Essentials

   4.0 out of 5 stars 

   Online Presentations | 24 Nov 2008 | Contributor(s):: Mark Lundstrom

   Outline: 1) The CMOS inverter,2) Speed,3) Power,4) Circuit performance,5) Metrics,6) Limits.This lecture is an overview of CMOS circuits. For a more detailed presentation, the following lectures from the Fall 2006 teaching of this course should be viewed:Lecture 24: CMOS Circuits, Part I (Fall...

7. ECE 612 Lecture 18B: CMOS Process Flow

   0.0 out of 5 stars 

   Online Presentations | 18 Nov 2008 | Contributor(s):: Mark Lundstrom

   For a basic, CMOS process flow for an STI (shallow trench isolation process), see: http://www.rit.edu/~lffeee/AdvCmos2003.pdf.This lecture is a condensed version of the more complete presentation (listed above) by Dr. Fuller.

8. ECE 612 Lecture 18A: CMOS Process Steps

   0.0 out of 5 stars 

   Online Presentations | 12 Nov 2008 | Contributor(s):: Mark Lundstrom

   Outline: 1) Unit Process Operations,2) Process Variations.

9. 

   jawar

   https://nanohub.org/members/21961

10. 

    Charles Augustine

    Charles Augustine (S’08-M’11) received the Bachelors in Electronics from BITS, Pilani, India in 2004 and the PhD degree in Electrical and Computer Engineering from Purdue University in...

    https://nanohub.org/members/18462

11. Computational Electronics

    4.5 out of 5 stars 

    Courses | 02 Jun 2006 | Contributor(s):: Dragica Vasileska

    Scaling of CMOS devices into the nanometer regime leads to increased processing cost. In this regard, the field of Computational Electronics is becoming more and more important because device simulation offers unique possibility to test hypothetical devices which have not been fabricated yet...