CMOS+X: Integrated Ferroelectric Devices for Energy Efficient Electronics

By Sayeef Salahuddin

Electrical Engineering and Computer Sciences, University of California, Berkeley, CA

Published on

Abstract

Despite ominous foretelling of a slowdown, over the last decade the computational throughput has increased by orders of magnitude. Energy efficiency is critical not only to maintain this incessant advancement, but also to ensure that electronics does not become a drag on the finite energy resources of the world. This will need a radical rethinking of the basic building blocks that constitute the electronic hardware. In this talk, I shall briefly present how integrated ferroelectric devices offer a new pathway in this context. First, I shall discuss the phenomenon of negative capacitance in ferroelectric materials. A fundamentally new state in the ferroelectrics, negative capacitance promises to reduce power consumption in electronic devices significantly. I shall discuss our current understanding of negative capacitance derived from numerous experimental works done over the last few years. We shall further discuss the material science that is enabling the integration of negative capacitance into advanced transistors. Going beyond transistors, the insight gained from physics and materials could also lead to advanced, low power memory devices. These examples underscore how functional augmentation of CMOS by harnessing new physical phenomena, we are calling it CMOS+X, could offer opportunities that are otherwise not available through conventional means.

Bio

Dr. Sayeef Salahuddin is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. His group explores physics for low power electronic and spintronic devices. He is mostly known for the discovery of the Negative Capacitance effect that shows substantial promise for logic, memory and energy storage devices. Salahuddin received the Presidential Early Career Award for Scientist and Engineers (PECASE) from President Obama. Salahuddin also received several other awards including the National Science Foundation CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Airforce Office of Scientific Research and the Army Research Office, and the IEEE George E Smith Award. Salahuddin is a co-director of the Berkeley Device Modeling Center (BDMC) and Berkeley Center for Negative Capacitance Transistors (BCNCT). Salahuddin is also a co-director of ASCENT, which is a flagship device technology effort in the US, jointly supported by SRC and DARPA. He served on the editorial board of IEEE Electron Devices Letters (2013-16) and was the chair the IEEE Electron D

 

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Cite this work

Researchers should cite this work as follows:

  • Sayeef Salahuddin (2022), "CMOS+X: Integrated Ferroelectric Devices for Energy Efficient Electronics," https://nanohub.org/resources/36734.

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Time

Location

Buton Morgian, 121, Purdue University, West Lafayette, IN

Tags

CMOS+X: Integrated Ferroelectric Devices for Energy Efficient Electronics
  • Integrated Ferroelectric Devices for Energy Efficient Electronics 1. Integrated Ferroelectric Devic… 0
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  • Information Processing 2. Information Processing 44.944944944944943
    00:00/00:00
  • Need for Energy Efficiency in Information Processing 3. Need for Energy Efficiency in … 102.8028028028028
    00:00/00:00
  • Functional Materials for Energy Efficient Computing 4. Functional Materials for Energ… 266.83350016683352
    00:00/00:00
  • Minimum Energy Dissipation in Switching 5. Minimum Energy Dissipation in … 286.25291958625291
    00:00/00:00
  • Overcoming Boltzmann Tyranny 6. Overcoming Boltzmann Tyranny 470.87087087087087
    00:00/00:00
  • Overcoming Boltzmann Tyranny 7. Overcoming Boltzmann Tyranny 525.32532532532537
    00:00/00:00
  • Dipolar Ordering and Ferroelectricity 8. Dipolar Ordering and Ferroelec… 577.84451117784454
    00:00/00:00
  • Negative Capacitance: Origin 9. Negative Capacitance: Origin 653.35335335335333
    00:00/00:00
  • Negative Capacitance: Origin 10. Negative Capacitance: Origin 684.51785118451789
    00:00/00:00
  • Negative Capacitance: Origin 11. Negative Capacitance: Origin 752.88621955288625
    00:00/00:00
  • Negative Capacitance: Energy considerations 12. Negative Capacitance: Energy c… 803.97063730397065
    00:00/00:00
  • Negative Capacitance: Energy considerations 13. Negative Capacitance: Energy c… 843.41007674341006
    00:00/00:00
  • Negative Capacitance: Energy considerations 14. Negative Capacitance: Energy c… 864.39773106439782
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  • Less energy at same Q 15. Less energy at same Q 902.0687354020688
    00:00/00:00
  • Less energy at same Q 16. Less energy at same Q 973.973973973974
    00:00/00:00
  • Changing the Field Effect in a FET 17. Changing the Field Effect in a… 1025.3253253253254
    00:00/00:00
  • Negative Capacitance 18. Negative Capacitance 1066.3329996663331
    00:00/00:00
  • Enhancement of Capacitance 19. Enhancement of Capacitance 1135.5355355355355
    00:00/00:00
  • Microscopic imaging of negative capacitance 20. Microscopic imaging of negativ… 1218.6186186186187
    00:00/00:00
  • Microscopic Imaging of Negative Capacitance 21. Microscopic Imaging of Negativ… 1273.9739739739741
    00:00/00:00
  • From Physics to Materials 22. From Physics to Materials 1461.5615615615616
    00:00/00:00
  • A Non-perovskite Ferroelectric Material 23. A Non-perovskite Ferroelectric… 1609.90990990991
    00:00/00:00
  • Ultra thin Ferroelectrics 24. Ultra thin Ferroelectrics 1666.3997330664
    00:00/00:00
  • World's Thinnest Ferroelectric on Silicon 25. World's Thinnest Ferroelectric… 1701.6349683016351
    00:00/00:00
  • How thin can one go? 26. How thin can one go? 1729.9632966299635
    00:00/00:00
  • Advanced Devices with NC gate stack 27. Advanced Devices with NC gate … 1761.7617617617618
    00:00/00:00
  • Advanced Devices with NC Gate Stack 28. Advanced Devices with NC Gate … 1844.5111778445112
    00:00/00:00
  • Negative Capacitance Gate Oxide 29. Negative Capacitance Gate Oxid… 2000.0667334000668
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  • MIT-LL Process Flow 30. MIT-LL Process Flow 2195.4954954954956
    00:00/00:00
  • Negative Capacitance in HZH | CMOS Integration at MIT LL R&D Foundry 31. Negative Capacitance in HZH | … 2253.4868201534869
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  • Lg = 90 nMOS Ion benchmarking 32. Lg = 90 nMOS Ion benchmarking 2302.8695362028698
    00:00/00:00
  • Going Beyond Logic Transistors 33. Going Beyond Logic Transistors 2451.4514514514517
    00:00/00:00
  • Device Physics of the FE Gate Memory 34. Device Physics of the FE Gate … 2599.8331664998332
    00:00/00:00
  • A Different Use of Negative Capacitance 35. A Different Use of Negative Ca… 2743.1431431431433
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  • A Different Use of Negative Capacitance 36. A Different Use of Negative Ca… 2779.5462128795461
    00:00/00:00
  • Optimizing the IL Layer 37. Optimizing the IL Layer 2809.90990990991
    00:00/00:00
  • Record Performance on a Memory Device 38. Record Performance on a Memory… 2849.1825158491824
    00:00/00:00
  • Compute in Memory 39. Compute in Memory 2938.0714047380716
    00:00/00:00
  • Negative Capacitance for Energy Storage 40. Negative Capacitance for Energ… 2988.4884884884887
    00:00/00:00
  • Negative Capacitance 41. Negative Capacitance 3059.75975975976
    00:00/00:00
  • From Physics, Materials to Devices 42. From Physics, Materials to Dev… 3101.6016016016019
    00:00/00:00
  • A Vision for the Future Information Processing Systems: CMOS+X 43. A Vision for the Future Inform… 3188.3883883883886
    00:00/00:00
  • Looking Forward: Open Platform of Innovation 44. Looking Forward: Open Platform… 3291.2245578912248
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