This is the second in a series of talks addressing “Device Options and Trade-offs for 5 nm CMOS technology. With continuous device down-scaling as predicted and required by Moore's law, silicon complementary metal-oxide-semiconductor (CMOS) technology has been pushed down to 10 nm, approaching its physical limitations. For further developments, novel channel materials, alternative switching mechanisms and new device structures are needed. High mobility materials such as Germanium p-channel and InGaAs n-channel MOSFETs have been widely discussed and investigated for post- Silicon technology. However, various problems still exist as showstoppers. For example, the complexity to integrate nanoscale Ge and InGaAs devices on the same 300 mm Si platform is a grand challenge to overcome. Ge on Silicon with its high electron mobility and hole mobility could be a simple solution for the development of a manufacturable technology. This talk will review recent progress as well as challenges on Ge research for future logic applications with emphasis on the breakthrough work at Purdue University on Ge nFET which leads to the demonstration of the world first Ge CMOS circuits on Si substrates. Ge device technology includes planar MOSFETs, FinFETs and nanowire FETs.

Dr. Peide (Peter) Ye is a Professor of Electrical and Computer Engineering and University Faculty Scholar at Purdue University in USA. He received his Ph.D. from the Max-Planck-Institute of Solid State Research, Stuttgart, Germany, in 1996. Before joining the Purdue faculty in 2005, he worked for NTT, NHMFL/Princeton University, and Bell Labs/Agere Systems. His current research is focused on ALD high-k integration on novel channel materials include III-V, Ge, complex oxides, graphene and other 2D crystals. He has authored and co-authored more than 300 peer reviewed articles and conference presentations. He is a Fellow of IEEE.

This work led by graduate student Mr. Heng Wu achieved the best student paper awards from 2014 VLSI Symposia and DRC 2015, Nicollian Award from IEEE SISC 2013.

NEEDS: Nano-Engineered Electronic Device Simulation Node, Discovery Park, Network for Computational Nanotechnology

Researchers should cite this work as follows:

• peide ye (2015), "Green Light on Germanium," https://nanohub.org/resources/23033.

  BibTex | EndNote

1. CMOS
2. devices
3. MOSFET
4. nanoelectronics