Verilog-A: Present Status and Guidelines

By Geoffrey Coram

Analog Devices, Inc., Wilmington, MA

Published on

Abstract

Verilog-A is the standard language for compact model development and implementation. This talk provides some background on the rationale for and development of Verilog-A, summarizes the current status of the language, and provides a short introduction and some tips for writing good compact models in Verilog-A. Pointers to more extensive references are also provided.

Bio

The presenter, Dr. Geoffrey Coram, works for Analog Devices, Inc. (ADI) in the CAD development group, improving ADI's internal circuit simulator and evaluating next-generation simulation tools. He has a particular focus on compact device models in Spice simulators and chaired the Accellera Verilog-AMS subcommittee for compact modeling extensions, which identified the extensions necessary for Verilog-AMS to become the standard, simulator-independent language for Spice modeling. Dr. Coram's co-author is Dr. Colin McAndrew of Freescale, who is known for many contributions to compact modeling and is a strong advocate of the use of Verilog-A.

Cite this work

Researchers should cite this work as follows:

  • Geoffrey Coram (2013), "Verilog-A: Present Status and Guidelines," https://nanohub.org/resources/18557.

    BibTex | EndNote

Time

Location

Massachusetts Institute of Technology, Cambridge, MA

Tags

Verilog-A: Present Status and Guidelines
  • Verilog-A: Present Status and Guidelines 1. Verilog-A: Present Status and … 0
    00:00/00:00
  • How to put a compact model into a simulator? 2. How to put a compact model int… 28.361695028361694
    00:00/00:00
  • History 3. History 108.07474140807474
    00:00/00:00
  • Hijacked 4. Hijacked 160.96096096096096
    00:00/00:00
  • CMC Standard Models 5. CMC Standard Models 216.64998331664998
    00:00/00:00
  • Problems With Verilog-A 6. Problems With Verilog-A 279.64631297964632
    00:00/00:00
  • Problems With Verilog-A 7. Problems With Verilog-A 301.70170170170172
    00:00/00:00
  • Verilog-A Performance 8. Verilog-A Performance 405.3053053053053
    00:00/00:00
  • Verilog-A Performance 9. Verilog-A Performance 515.14848181514856
    00:00/00:00
  • Newton-Raphson Limiting 10. Newton-Raphson Limiting 877.877877877878
    00:00/00:00
  • Newton-Raphson Limiting 11. Newton-Raphson Limiting 921.98865532198874
    00:00/00:00
  • Recommended Best Practices 12. Recommended Best Practices 1026.8268268268269
    00:00/00:00
  • Verilog-A Recommended Practices 13. Verilog-A Recommended Practice… 1086.4531197864533
    00:00/00:00
  • A Few Coding Guidelines for Compact Models 14. A Few Coding Guidelines for Co… 1124.5912579245912
    00:00/00:00
  • Coding Style 15. Coding Style 1240.6406406406406
    00:00/00:00
  • Coding Style: R2_CMC 16. Coding Style: R2_CMC 1291.9586252919587
    00:00/00:00
  • Coding Discipline 17. Coding Discipline 1345.6456456456458
    00:00/00:00
  • Functions and Derivatives 18. Functions and Derivatives 1399.8998998999
    00:00/00:00
  • Memory States 19. Memory States 1535.2686019352686
    00:00/00:00
  • Numbers 20. Numbers 1582.7494160827496
    00:00/00:00
  • Optimizations 21. Optimizations 1644.3443443443443
    00:00/00:00
  • A Few Comments on Debugging 22. A Few Comments on Debugging 1785.4521187854523
    00:00/00:00
  • Conclusion 23. Conclusion 1895.6956956956958
    00:00/00:00