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Digital design flow is a lengthy process that involves many steps to take the design from RTL to a working silicon. The objective of this course is to demystify this field and provide in-depth understanding of the different transformations in each design step, how these transformations can affect the final performance metrics, and how to tune the process to meet design specs.

Specifically, this course focuses on fundamental elements in the design process, including HDL modeling, event-driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, signoff checks, and test planning. Throughout the course, attendees learn the salient differences in these elements when using FPGA and ASIC platforms. Both Xilinx (for FPGA) and Cadence (for ASIC) design flows are utilized as part of the training vehicle. VIVADO from Xilinx to cover the entire FPGA flow. On the Cadence side, ASIC simulations is demonstrated using Incisive, while Genus is used for synthesis, and Innovus for physical implementation. Finally, Mentor Graphics’ Calibre is used for ASIC signoff checks. The course contains a demonstration project, which is progressively developed by the trainees throughout the course modules to exercise the two digital design flows. The goal of this course is to provide attendees with understandings of FPGA and ASIC digital flows and to support this understanding with hands-on experience of tools used by the industry.

Intended Learning Outcomes (ILOs):
Upon the completion of this course, trainees should be able to:

   • Holistically understand digital design flow (from the specification phase to the signoff checks).
   • Learn all transformations occur during the design flow and analyze their effect on performance metrics.
   • Gain knowledge on different technology files and standard cell views.
   • Identify different design flows based on the target implementation technology (ASIC vs. FPGA).
   • Understand timing-analysis and timing-closure in different design phases.
   • Understand chip level planning (Power Distribution Network, IO, Global Signals, etc).
   • Design meaningful digital blocks starting from RTL and taking them to Bitstream or GDSII.

Target Audience:

Entry-level design engineers who want to grasp the full digital design cycle, senior undergraduate and post-graduate students (who are preparing to get involved in digital IC design, research and development, hardware test), product and verification engineers as well as system and computer architecture engineers.

Course topics:

1. Module-I: Fundamentals (40%):
   • Digital vs Analog.
   • Architecture of digital circuits (Delays, data path, control path, synchronization, data encoding).
   • Digital System Design (Microprocessors, FPGA, ASIC).
   • Fundamentals of digital design (HDL modeling, synthesis, timing analysis and timing closure, physical design, chip planning, signoff checks)
   Hands-on Lab:
   • Analyzing and comparing analog vs digital signals over oscilloscopes to understand the analog side of digital signals (video demonstration).
   • Building very simple processor to understand the fundamentals of digital design and the fundamentals of HDL.
2. Module-II: FPGA based design (25%):
   • What is an FPGA?
   • FPGA fabric architectures.
   • HDL modeling and Synthesis for FPGA.
   • FPGA types and applications (eFPGAs, Hardware acceleration, ASIC prototyping, etc.).
   Hands-on Lab:
   • Synthesize a simple processor for FPGA and understand the resultant synthesized HDL and how FPGA bit stream works.
   • Detailed comparison between different FPGA fabrics based on vendors and families.
3. Module-III: ASIC design (35%):
   • Components of process design kits (PDKs).
   • What are standard cells and standard cell views?
   • Types of digital synthesis.
   • Timing analysis (STA, SSTA).
   • Physical design (floorplanning, power planning, Clock Tree Synthesis (CTS), and timing closure)
   • Chip level planning (I/O, power planning, chip testing)
   • Signoff checks (DRC, LVS, …)
   • GDSII.
   • Preparing for chip testing, Dos and Don’ts.
   Hands-on Lab:
   • Model a basic processor for ASIC and understand HDL coding style for ASIC vs FPGA.
   • Examine all the files in the design kit/standard cell views and understand the information provided in each file type.
   • Synthesize the processor and understand the different transformations occur with each design step.
   • Implement the physical design and signoff check steps and generate the GDSII of the processor.

Course Facilities:
Throughout the course, trainees will have access to the following computer software:

• Access to VIVADO from Xilinx; Incisive, Genus, Innovus, from Cadence, Modelsim and Calibre from Mentor Graphics.
• Access to SKY130 (PDK) that includes standard cells library.

Course Perquisites:

Basic understanding of Digital Logic and Computer Architecture is preferable.