Graphene Switch Box

By Sansiri Tanachutiwat1; wei wang2

1. College of Nanoscale Science and Engineering, University at Albany, Albany, NY, USA 2. CNSE, University at Albany

Graphene Switch Box for FPGA Interconnects

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Version 1.0w - published on 17 Mar 2015

doi:10.4231/D3599Z28J cite this

This tool is closed source.

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Usage

World usage

Location of all "Graphene Switch Box" Users Since Its Posting

Cumulative Simulation Users

75

6 7 9 10 12 14 16 17 19 22 23 25 26 26 27 27 28 28 29 31 32 32 33 33 33 33 33 34 35 35 35 35 36 37 37 37 37 38 43 44 46 47 47 48 48 49 49 49 49 49 49 51 52 52 52 53 53 53 54 54 54 55 55 55 55 55 55 55 55 57 57 57 57 57 58 59 60 60 60 61 61 61 61 61 61 61 61 61 61 61 61 61 62 62 62 62 62 64 64 64 64 64 64 64 65 65 65 65 65 65 65 65 65 65 65 65 67 67 67 67 67 68 68 68 69 69 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 72 72 72 72 73 73 73 73 73 73 73 73 73 73 74 75 75

Simulation Runs

196

52 53 58 60 64 77 81 84 86 94 95 106 107 107 112 112 113 113 115 121 122 122 124 124 125 125 125 127 132 132 132 132 133 134 134 134 134 98 109 110 112 114 114 115 115 119 119 119 119 119 119 121 123 124 124 128 128 128 129 129 129 131 131 131 131 131 131 131 131 135 135 135 135 135 136 138 140 140 140 142 142 142 142 142 142 142 142 142 142 142 142 142 144 144 144 144 144 147 147 147 147 147 147 147 148 148 148 148 148 148 148 148 148 149 148 148 152 152 152 152 152 153 153 153 161 161 187 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 188 189 189 189 189 192 192 192 192 192 192 192 192 192 192 194 196 196
Overview
Average Total
Wall Clock Time 1.71 hours 8.99 days
CPU time 1.19 seconds 2.51 minutes
Interaction Time 6.02 minutes 12.65 hours