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Cadence digital device simulation contains a suite of Cadence electronic design automation (EDA) tools for developing digital designs using a hardware description language, verifying their behavior, and synthesizing the register-transfer-level (RTL) design to a gate-level netlist to accurately model timing.

The tool includes Cadence Xcelium which allows the user to simulate and test a design from its source code or gate-level netlist and view signal waveforms to debug and verify the design. The tool also includes Cadence Genus which synthesizes RTL code into a gate-level netlist for use in further simulation and in physically placing and routing the design for eventual fabrication.

Cadence electronic design automation: https://www.cadence.com

Tool deployment supported by the Network for Computational Nanotechnology and Purdue University.

Researchers should cite this work as follows:

• Steven Clark, Alejandro Strachan (2024), "Cadence digital device simulation," https://nanohub.org/resources/cadencedigital. (DOI: 10.21981/M039-ZT39).

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1. chipsHUB content
2. commercial tools available on nanoHUB
3. SCALE (Scalable Asymmetric Lifecycle Engagement)
4. semiconductors