Sending report ...NCN Nanoelectronics: Simulation Tools for Research
Schred
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Usage Stats Last 12 Months: Updated 16 May, 2008 more › Users: 532 Jobs: 10412 Avg. exec. time: 48 secs Reviews & Citations Google/IEEE: updated 25 Apr, 2008 Avg. Review: Citations: 74
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| Contributor(s) | Dragica Vasileska Arizona State University Shaikh S. Ahmed, Matteo Mannino, Akira Matsudaira, Gerhard Klimeck Purdue University, West Lafayette |
|---|---|
| At a glance | Solves Schrodinger/Poisson equations for a 1D quantum well, as you might have MOSFET, SOS, or SOI structure. |
| Screenshots | |
| Description | Schred 2.0 calculates the envelope wavefunctions and the corresponding bound-state energies in a typical MOS (Metal-Oxide-Semiconductor) or SOS (Semiconductor-Oxide- Semiconductor) structure and a typical SOI structure by solving self-consistently the one-dimensional (1D) Poisson equation and the 1D Schrodinger equation. |
| Cite this work | If you reference this work in a publication, please cite as follows:
In addition, we would appreciate it if you would add the following acknowledgment to your publication:
|
| Date posted | 09 Feb, 2006 |
| Type | Tools |
| Tags |
Citations
The following are publications that have cited this resource, separated by their affiliation to the NCN.
Non-affiliated authors
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Ohata, A.; Casse, M.; Faynot, O. (2008), "Electrical Characteristics Related to Silicon Film Thickness in Advanced FD SOI-MOSFETs", Solid-State Electronics, 52, 1: pg. 126-133, January.
-
Ray, B.; Shubhakar; Mahapatra, S. (2007), "Necessity for Quantum MEchanical Simulation for the Future Technology Nodes", Physics of Semiconductor Devices, 2007. IWPSD 2007. International Workshop on: pg. 880-883, December. 978-1-4244-1728-5. (DOI: 10.1109/IWPSD.2007.4472662).
-
Bhattacherjee, S.; Biswas, A. (2007), "Modeling of Threshold Voltage and Subthreshold Slope of Nanoscale DG MOSFETs", Semiconductor Science and Technology, 23, December.
-
von Haartman, M.; Ostling, M. (2007), "Effect of Channel Positioning on the 1/f noise in Silicon-on-Insulator Metal-Oxide-semiconductor Field-Effect Transistors", Journal of Applied Physics, 101, February.
-
Eminente, S.; Cristoloveanu, S.; Clerc, R.; Ohata, A.; Ghibaudo, G. (2007), "Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects", Solid-State Electronics, 51, 2: pg. 239-244, February.
-
Li, M.; Yu, Z. (2007), "Compact Modeling for Inversion Charge in Nanoscale DG-MOSFETs", Chinese Journal of Semiconductors, 28, 11: pg. 1717-1721, July.
-
Goodnick, S. (2007), "Transport in Nanostructures: A Tutorial", Nano and Giga Challenges in Electronics and Photonics, Symposium and Spring School (Tutorial Lectures), Phoenix, AR, March.
-
Lazaro, A.; Nae, B.; Moldovan, O.; Inigez, B. (2007), "A Compact Quantum Model of Nanoscale Double-Gate MOSFET for RF and Noice Simulations", Electron Devices, 2007 Spanish Conference on: pg. 355-358, Madrid, February. 1-4244-0868-7. (DOI: 10.1109/SCED.2007.384067).
-
Barin, N.; Braccioli, M.; Fiegna, C.; Sangiorgi, E. (2007), "Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs", Nantechnology, IEEE Transactions on, 6, 4: pg. 421-430, July. 1536-125X. (DOI: 10.1109/TNANO.2007.894022).
-
Gomez, L.; Aberg, I.; Hoyt, J.L. (2007), "Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs with Body Thickness Ranging from 2 - 2 nm", Electron Devices, IEEE Transactions on, 28, 4: pg. 285-287, April.
-
Granzner, R.; Schwierz, F.; Polyakov, V.M. (2007), "An Analytical Model for the Threshold Voltage Shift Caused by Two-Dimensional Quantum Confinement in Undoped Multi-Gate MOSFETs", Electron Devices, IEEE Transactions on, 54, 9: pg. 2562-2565, September. 1557-9646. (DOI: 10.1109/TED.2007.902167).
-
Cumberbatch, E.; Uno, S.; Abebe, H. (2007), "Nano-scale MOSFET device modelling with quantum mechanical effects", European Journal of Applied Mathematics.
-
von Haartman, M.; Östling, M. (2007), "Effect of channel positioning on the 1/f noise in silicon-on-insulator metal-oxide-semiconductor field-effect transistors", J. Appl. Phys., 101, 034506.
-
Entner, R.; Heinzl, R.; Nentchev, A.; Ungersboeck, E.; Wagner, S.; Selberherr, S. (2006), "VISTA Status Report", Institute for Microelectronics, Technical University Vienna, December.
-
Morris, H.; Limon, A. (2006), "Quantum Corrections: a Multilevel Solver for the Density-Gradient Equation", International Journal of Computational Science and Engineering, 2, 3-4: pg. 119-128.
-
Antoniadis, D. A.; Aberg, I.; Ni Chleirigh, C.; Nayfeh, O. M.; Khakifrooz, A.; Hoyt, J. L. (2006), "Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations", IBM Journal of Research and Development, 50, 4/5, July/September.
-
Wong, M.; Shi, X.; Chow, T. (2006), "On the Body-Thickness Dependence of the Linear Extrapolated Threshold Voltage of a Double-Gate Metal-Oxide-Semicondcutor Field-Effect Device", Japanese Journal of Applied Physics, 45, 12: pg. 9069-9071, October.
-
Wang, L (2006), "Quantum Mechanical Effects on MOSFET Scaling Limit" (PhD Thesis), Georgia Institute of Technology, August.
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Ge, L.; Gamiz, F; Workman, G. O.; Veeraraghavan, S. (2006), "On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs", Electron Devices, IEEE Transactions on, 53, 4: pg. 753-758, April.
-
Li, M.; Yu, Z. (2006), "Analytical Quantum Modeling of Inversion Charge Density for Nanoscale Undoped Symmetric DG-MOSFETs", Solid-State and Integrated Circuit Technology, 2006, ICSICT '06 International Conference on: pg. 1361-1363, Shanghai, China, October. 1-4244-0160-7. (DOI: 10.1109/ICSICT.2006.306183).
-
Limon, A.; Morris, H. (2006), "A multilevel adaptive solver based on second-generation wavelet thresholding techniques", Numerical Linear Algebra with Applications, 13, 2-3: pg. 251-273, February. (DOI: 10.1002/nla.479).
-
Bandi, S.P.R.; Washburn, C.; Mukund, P.R.; Kolnik, J.; Paradis, K.; Howard, S.; Burleson, J. (2006), "Effect of gate poly-silicon depletion on MOSFET input impedance", IEEE Microwave and Wireless Components Letters, 16, 5.
-
Uno, S.; Abebe, H.; Cumberbatch, E. (2006), "Analytical Formulae of Quantum-Mechanical Electron Density in Inversion Layer in Planar MOSFETs", IWCM 2006: pg. 25, January.
-
Ungersboeck, E.; Kosina, H. (2006), "Monte Carlo study of electron transport in strained silicon inversion layers", Journal of Computational Electronics, 5, 2-3: pg. 79-83, July.
-
von Hartmaan, M. (2006), "Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors" (PhD Thesis), Royal Institute of Technology (KTH), Stockholm, Sweden.
-
Ritenour, A.; Khakifirooz, A.; Antoniadis, D.A.; Lei, R.Z.; Tsai, W.; Dimoulas, A.; Mavrou, G.; Panayiotatos, Y. (2006), "Subnanometer-equivalent-oxide-thickness germanium p-metal-oxide-semiconductor field effect transistors fabricated using molecular-beam-deposited high-k/metal gate stack", Appl. Phys. Lett., 88, 132107.
-
Avila, L.; Franklin, M. (2006), "Quantum Corrections to Threshold Voltages For Decanano MOSFETs", Final Report, May 2006 to USC – Information Sciences Institute, May.
-
Dawei, Z.; Lilin, T.; Zhiping, Y. (2005), "Analytical Modeling of Threshold Voltage for Double-Gate MOSFET Fully Comprising Quantum Mechanical Effects", Chinese Journal of Semiconductors, 26, 3, March.
-
Trivedi, V.P.; Fossum, J. G. (2005), "Quantum-mechanical effects of the threshold voltage of undoped double-gate MOSFETs", Electron Device Letters, IEEE, 26, 8: pg. 579-582, August.
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Kim, K.; Das, K.K.; Joshi, R.V.; Chuang, C.-T. (2005), "Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits", Electron Devices, IEEE Transactions on, 52, 5: pg. 980-986, May.
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Lauer, I.; Antoniadis, D.A. (2005), "Enhancement of Electron Mobility in Ultrathin-Body Silicon-on-Insulator MOSFETs with Uniaxial Strain", Electron Device Letters, IEEE, 26, 5: pg. 314-316, May.
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Barin, N.; Braccioli, M.; Fiegna, C.; Sangiorgi, E. (2005), "Scaling the High-Performance Double-Gate SOI MOSFET down to 32 nm Technology Node with SiO/sub2/-based Gate Stacks", Electron Devices Meeting, 2005, IEDM Technical Digest, IEEE International: pg. 609-612, December.
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Kim, K.; Hanafi, H.I.; Cai, J.; Chuang, C.-T. (2005), "Off-State Current and Performance Analysis for Doubl-Gated CMOS with Non-Self-Aligned Back Gate", Electron Devices, IEEE Transactions on, 52, 9: pg. 2104-2107, September.
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Ungersboeck, E.; Kosina, H. (2005), "The Effect of Degeneracy on Electron Transport in Strained Silicon Inversion Layers", Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on: pg. 311-314, Tokyo, Japan, September.
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Ceric, H.; Karner, M.; Nentchev, A.; Schwaha, P.; Ungersboeck, E.; Selberherr, S. (2005), "Vista Status Report", institute for Microelectronics, Technical University Vienna.
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Shi, X.; Wong, M. (2005), "Effects of substrate doping on the linearly extrapolated threshold voltage of symmetrical DG MOS devices", IEEE Transactions on Electron Devices, 52, 7, July.
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Aberg, I.; Hoyt, J.L. (2005), "Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm", IEEE Electron Device Letters, 26, 9.
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Shi, X.; Wong, M. (2005), "On the threshold voltage of metal–oxide–semiconductor field-effect transistors", Solid-State Electronics, 49, 7.
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Zhang, D.; Yu, Z.; Tian, L. (2005), "A Compact IV Model for FinFETs Comprising Multi-Dimensional Electrostatics and Quantum Mechanical Effects", Technical Proceedings of the 2005 Workshop on Compact Modeling: pg. 191-194. 0-9767985-3-0.
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Tang, T.W.; O'Regan, T.; Wu, B. (2004), "Thomas-Fermi Approximation for a Two-Dimensional Electron Gas at Low Temperatures", Journal of Applied Physics, 95, 12: pg. 71-73, June.
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Choi, Y.K. (2004), "FinFET for Terabit Era", Journal of Semiconductor Technolgoy and Science, 4, 1, March.
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Khakifrooz, A.; Nayfeh, O. M.; Antoniadis, D. A. (2004), "Assessing the Performance Limits of Ultra-Thin Double-Gate MOSFETs: Silicon vs. Germanium", SOI Conference, 2004, Proceedings. 2004 IEEE International: pg. 79-80, October.
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Trivedi, V.P.; Fossum, J. G.; Gamiz, F. (2004), "A Compact QM-Based Mobility Model for Nanoscale Ultra-Thin-Body CMOS Devices", Electron Devices Meeting, 2004, IEDM Technical Digest, IEEE International: pg. 763-766, December. 0-7803-8684-1. (DOI: 10.1109/IEDM.2004.1419284).
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Fossum, J. G.; Ge, L.; Chiang, M.-H.; Trivedi, V. P.; Chowdhury, M. M.; L. Matthew; Workman, G. O.; Nguyen, B.-Y. (2004), "A process/physics-based compact model for nonclassical SMOS device and circuit design", Solid-State Electronics, 48, 6: pg. 919-926, June. (DOI: 10.1016/J.sse.2003.12.030).
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Yu, Y.S.; Kim, S.H.; Choi, B.H.; Hong, S.H.; Hwang, S.W.; Ahn, D. (2004), "SPICE-Compatible Floating-Dot Single-Electron Memory Model with a New Description of SOI MOSFETs Including Quantum-Mechanical Effects", Journal of Korean Physcal Society, 44, 1: pg. 117-120, January.
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Khakifirooz, A.; Antoniadis, D.A. (2004), "On the electron mobility in ultrathin SOI and GOI", IEEE Electron Device Letters, 25, 2: pg. 80-82, February.
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Ha, Daewon; Takeuchi, H.; Choi, Yang-Kyu; King, Tsu-Jae (2004), "Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs", IEEE Transactions on Electron Devices, 51, 12: pg. 1989-1996, December.
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Mohaidat, J.M.; Ahmad-Bitar, R.N. (2004), "Parameters affecting the accuracy of oxide thickness prediction in thin metal–oxide–semiconductor structures", Superlattices and Microstructures, 35, 1-2: pg. 85-94, February.
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Barin, N.; Fiegna, C.; Sangiorgi, E. (2004), "Analysis of strained-silicon-on-insulator double-gate MOS structures", 34th European Solid-State Device Research conference, 2004: pg. 169-172, September. 0-7803-8478-4. (DOI: 10.1109/ESSDER.2004.1356516).
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Ha, D.; Takeuchi, H.; Choi, Y.-K.; King, T.-J.; Bai, W.P.; Kwong, D.L.; Agarwal, A.; Ameen, M. (2004), "Molybdenum gate HfO2 CMOS FinFET technology", Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International.
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Kim, K.; Fossum, J. G. (2003), "Achieving the ballistic-limit current in Si MOSFETs", Solid-State Electronics, 47, 4: pg. 721-726, April. (DOI: 10.1016/S0038.1101(02)00330-1).
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Wang. L.; Chen, Q.; Murali, R.; Meindi, J. D. (2003), "Quantum Mechanical Effects on CMOS SOC Performance", SOC Conference, 2003, Proceedings, IEEE International [Systems-on-Chip]: pg. 109-112, September.
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Krishnamohan, T.; Jungemann, C.; Saraswat, K.C. (2003), "A Novel, Very High Performance, Sub-20nm Depletion-Mode Double-Gate (DMDG) Si/Si/subx/Ge/sub (1-x)//Si Channel PMOSFET", Electron Devices Meeting, 2003, IEDM '03 Technical Digest, IEEE International: pg. 29.3.1-29.3.4, December. 0-7803-7872-5. (DOI: 10.1109/IEDM.2003.1269373).
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Ge, L.; Fossum, J.L.; Gamiz, F. (2003), "Mobility Enhancement via Volume Inversion in Double-Gate MOSFETs", SOI Conference, 2003, IEEE International: pg. 153-154, Newport Beach, California, October.
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Connelly, D.; Yu, Z.; Yergeau, D. (2002), "Quantum Simulation of Nanoscale Surround-Gate MOS Devices", IEEE Transactions on Electron Devices, January.
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Chang, L.; Yang, K.J.; Yeo, Yee-Chia; Polishchuk, I.; King, Tsu-Jae; Hu, Chenming (2002), "Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs", IEEE Transactions on Electron Devices, 49, 12, December.
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Choi, Y.; King, T.; Hu, C. (2002), "Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era", Solid-State Electronics, 46, 10: pg. 1595--1601, October.
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Connelly, D.; Yu, Z.; Yergeau, D. (2002), "Macroscopic simulation of quantum mechanical effects in 2-D MOSdevices via the density gradient method", Electron Devices, IEEE Transactions on, 49, 4: pg. 619--626, April.
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Ge, L.; Fossum, J. G. (2001), "Exploitation of volume inversion in optimal DG MOSFET design", SOI Conference, 2001 IEEE International, Durango, CO, USA, October.
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Richter, C.A.; Vogel, E.M. , Hodge, A.M.; Hefner, A.R. (2001), "Differences Between Quantum-Mechanical Capacitance-Voltage Simulators", Simulation of Semiconductor Processes and Devices 2001: Sispad 01.
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Kim, K.; Fossum, J.G. (2001), "Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices", Electron Devices, IEEE Transactions on, 48, 2: pg. 294-299, February.
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Choi, Y.-K; King, T.-J.; Hu, C. (2001), "Spacer FinFET: nano-scale CMOS technology for the terabit era", 2001 International Semiconductor Device Research Symposium: pg. 543-546, December. 0-7803-7432-0. (DOI: 10.1109/ISDRS.2001.984573).
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Chang, L.; Yang, K.J.; Yeo, Y.-C.; Choi, Y.-K.; King, T.-K.; Hu, C. (2001), "Reduction of direct-tunneling gate leakage current in double-gateand ultra-thin body MOSFETs", International Electron Devices Meeting, 2001. IEDM Technical Digest.
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Ge, L.; Fossum, J.L. (2000), "A Novel Compact Model of Quantum Effects in Scaled SOI and Double-Gate MOSFETs", SOI Conference, 2000, IEEE International: pg. 114-115, Wakefield, Massachusetts, October. 0-7803-6389-2. (DOI: 10.1109/SOI.2000.892796).
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Alam, M.K.; Khosru, Q.D.M., "Self-Consistent Modeling of Ultra Thin Body Double Gate MOSFET", Electron Devices and Solid-State Circuits, 2007. EDSSC 2007, IEE Eonference on: pg. 601-604.
Affiliated authors
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Alam, M.K.; Alam, A.; Ahmed, S.; Rabbani, M.G.; Khosru, Q.D.M. (2007), "Wavefunction Penetration Effect on C-V Characteristic of Double Gate MOSFET", Semiconductor Device Research Symposium, 2007 International: pg. 1-2, December.
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Mukhopadhyay, S.; Kim, K.; Kim, J.; Lo, H.-H.; Joshi, R.; Chuang, C.-T.; Roy, K. (2007), "Estimation of Gate-to-Channel Tunneling Current in Ultra-Thin Oxide sub-50 nm Double Gate Devices", Microelectronics Hournal, 38, 8-9: pg. 931-941, September.
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Ahmed, S.; Klimeck, G.; Kearney, D.; McLennan, M.; Anantram, M.P. (2007), "Quantum Simulations of Dual Gate MOSFET Devices: Building and Deploying Community Nanotechnology Software Tools on nanoHUB.org", International Journal of High Speed Electronics and Systems, 17, 3: pg. 485-494, September.
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Lundstrom, M.S.; Cantley, K.D.; Pal, H.S. (2007), "Nanoscale Transistors: Physics and Materials", The Materials Research Society: The Materials Gateway, 958.
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Mukhopadhyay, S.; Kim, K.; Chuang, C.T.; Roy, K. (2006), "Modeling and Analysis of Leakage Currents in Double-Gate Technologies", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transaction on, 25, 10: pg. 2052-2061, October.
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Mukhopadhyay, S.; Kim, K.; Kim, J.-J.; Lo, S.-H.; Joshi, R.V.; Chuang, C.-T.; Roy, K. (2005), "Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits.", Sixth International Symposium on Quality of Electronic Design, 2005. ISQED 2005.
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Mukhopadhyay, S.; Kim, K.; Chuang, C.-T.; Roy, K. (2005), "Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits", The 2005 International Symposium on Low Power Electronics and Design: pg. 8-13. 1-59593-137-6. (DOI: 10.1145/1077603.1077608).
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Ren, Z.; Hegde, S.; Doris, B.; Oldiges, P.; Kanarsky, T.; Dokumaci, O.; Roy, R.; Leong, M.; Jones, E.C.; Wong, H.-S.P. (2002), "An Experimental Study on Transport Issues and Electrostatics of Ultrathin Body SOI pMOSFETs", Electron Device Letters, IEEE, 23, 10: pg. 609-611, October. 1558-0563. (DOI: 10.1109/LED.2002.803757).
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Rumsey, D. (2001), "Electrical Characterization of Bulk MOSFETs in Terms of Backscattering Coefficients" (Master's Thesis), Purdue University, December.
Ohata, A.; Casse, M.; Faynot, O. (2008), "Electrical Characteristics Related to Silicon Film Thickness in Advanced FD SOI-MOSFETs", Solid-State Electronics, 52, 1: pg. 126-133, January.
Ray, B.; Shubhakar; Mahapatra, S. (2007), "Necessity for Quantum MEchanical Simulation for the Future Technology Nodes", Physics of Semiconductor Devices, 2007. IWPSD 2007. International Workshop on: pg. 880-883, December. 978-1-4244-1728-5. (DOI: 10.1109/IWPSD.2007.4472662).
Bhattacherjee, S.; Biswas, A. (2007), "Modeling of Threshold Voltage and Subthreshold Slope of Nanoscale DG MOSFETs", Semiconductor Science and Technology, 23, December.
von Haartman, M.; Ostling, M. (2007), "Effect of Channel Positioning on the 1/f noise in Silicon-on-Insulator Metal-Oxide-semiconductor Field-Effect Transistors", Journal of Applied Physics, 101, February.
Eminente, S.; Cristoloveanu, S.; Clerc, R.; Ohata, A.; Ghibaudo, G. (2007), "Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects", Solid-State Electronics, 51, 2: pg. 239-244, February.
Li, M.; Yu, Z. (2007), "Compact Modeling for Inversion Charge in Nanoscale DG-MOSFETs", Chinese Journal of Semiconductors, 28, 11: pg. 1717-1721, July.
Goodnick, S. (2007), "Transport in Nanostructures: A Tutorial", Nano and Giga Challenges in Electronics and Photonics, Symposium and Spring School (Tutorial Lectures), Phoenix, AR, March.
Lazaro, A.; Nae, B.; Moldovan, O.; Inigez, B. (2007), "A Compact Quantum Model of Nanoscale Double-Gate MOSFET for RF and Noice Simulations", Electron Devices, 2007 Spanish Conference on: pg. 355-358, Madrid, February. 1-4244-0868-7. (DOI: 10.1109/SCED.2007.384067).
Barin, N.; Braccioli, M.; Fiegna, C.; Sangiorgi, E. (2007), "Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs", Nantechnology, IEEE Transactions on, 6, 4: pg. 421-430, July. 1536-125X. (DOI: 10.1109/TNANO.2007.894022).
Gomez, L.; Aberg, I.; Hoyt, J.L. (2007), "Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs with Body Thickness Ranging from 2 - 2 nm", Electron Devices, IEEE Transactions on, 28, 4: pg. 285-287, April.
Granzner, R.; Schwierz, F.; Polyakov, V.M. (2007), "An Analytical Model for the Threshold Voltage Shift Caused by Two-Dimensional Quantum Confinement in Undoped Multi-Gate MOSFETs", Electron Devices, IEEE Transactions on, 54, 9: pg. 2562-2565, September. 1557-9646. (DOI: 10.1109/TED.2007.902167).
Cumberbatch, E.; Uno, S.; Abebe, H. (2007), "Nano-scale MOSFET device modelling with quantum mechanical effects", European Journal of Applied Mathematics.
von Haartman, M.; Östling, M. (2007), "Effect of channel positioning on the 1/f noise in silicon-on-insulator metal-oxide-semiconductor field-effect transistors", J. Appl. Phys., 101, 034506.
Entner, R.; Heinzl, R.; Nentchev, A.; Ungersboeck, E.; Wagner, S.; Selberherr, S. (2006), "VISTA Status Report", Institute for Microelectronics, Technical University Vienna, December.
Morris, H.; Limon, A. (2006), "Quantum Corrections: a Multilevel Solver for the Density-Gradient Equation", International Journal of Computational Science and Engineering, 2, 3-4: pg. 119-128.
Antoniadis, D. A.; Aberg, I.; Ni Chleirigh, C.; Nayfeh, O. M.; Khakifrooz, A.; Hoyt, J. L. (2006), "Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations", IBM Journal of Research and Development, 50, 4/5, July/September.
Wong, M.; Shi, X.; Chow, T. (2006), "On the Body-Thickness Dependence of the Linear Extrapolated Threshold Voltage of a Double-Gate Metal-Oxide-Semicondcutor Field-Effect Device", Japanese Journal of Applied Physics, 45, 12: pg. 9069-9071, October.
Wang, L (2006), "Quantum Mechanical Effects on MOSFET Scaling Limit" (PhD Thesis), Georgia Institute of Technology, August.
Ge, L.; Gamiz, F; Workman, G. O.; Veeraraghavan, S. (2006), "On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs", Electron Devices, IEEE Transactions on, 53, 4: pg. 753-758, April.
Li, M.; Yu, Z. (2006), "Analytical Quantum Modeling of Inversion Charge Density for Nanoscale Undoped Symmetric DG-MOSFETs", Solid-State and Integrated Circuit Technology, 2006, ICSICT '06 International Conference on: pg. 1361-1363, Shanghai, China, October. 1-4244-0160-7. (DOI: 10.1109/ICSICT.2006.306183).
Limon, A.; Morris, H. (2006), "A multilevel adaptive solver based on second-generation wavelet thresholding techniques", Numerical Linear Algebra with Applications, 13, 2-3: pg. 251-273, February. (DOI: 10.1002/nla.479).
Bandi, S.P.R.; Washburn, C.; Mukund, P.R.; Kolnik, J.; Paradis, K.; Howard, S.; Burleson, J. (2006), "Effect of gate poly-silicon depletion on MOSFET input impedance", IEEE Microwave and Wireless Components Letters, 16, 5.
Uno, S.; Abebe, H.; Cumberbatch, E. (2006), "Analytical Formulae of Quantum-Mechanical Electron Density in Inversion Layer in Planar MOSFETs", IWCM 2006: pg. 25, January.
Ungersboeck, E.; Kosina, H. (2006), "Monte Carlo study of electron transport in strained silicon inversion layers", Journal of Computational Electronics, 5, 2-3: pg. 79-83, July.
von Hartmaan, M. (2006), "Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors" (PhD Thesis), Royal Institute of Technology (KTH), Stockholm, Sweden.
Ritenour, A.; Khakifirooz, A.; Antoniadis, D.A.; Lei, R.Z.; Tsai, W.; Dimoulas, A.; Mavrou, G.; Panayiotatos, Y. (2006), "Subnanometer-equivalent-oxide-thickness germanium p-metal-oxide-semiconductor field effect transistors fabricated using molecular-beam-deposited high-k/metal gate stack", Appl. Phys. Lett., 88, 132107.
Avila, L.; Franklin, M. (2006), "Quantum Corrections to Threshold Voltages For Decanano MOSFETs", Final Report, May 2006 to USC – Information Sciences Institute, May.
Dawei, Z.; Lilin, T.; Zhiping, Y. (2005), "Analytical Modeling of Threshold Voltage for Double-Gate MOSFET Fully Comprising Quantum Mechanical Effects", Chinese Journal of Semiconductors, 26, 3, March.
Trivedi, V.P.; Fossum, J. G. (2005), "Quantum-mechanical effects of the threshold voltage of undoped double-gate MOSFETs", Electron Device Letters, IEEE, 26, 8: pg. 579-582, August.
Kim, K.; Das, K.K.; Joshi, R.V.; Chuang, C.-T. (2005), "Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits", Electron Devices, IEEE Transactions on, 52, 5: pg. 980-986, May.
Lauer, I.; Antoniadis, D.A. (2005), "Enhancement of Electron Mobility in Ultrathin-Body Silicon-on-Insulator MOSFETs with Uniaxial Strain", Electron Device Letters, IEEE, 26, 5: pg. 314-316, May.
Barin, N.; Braccioli, M.; Fiegna, C.; Sangiorgi, E. (2005), "Scaling the High-Performance Double-Gate SOI MOSFET down to 32 nm Technology Node with SiO/sub2/-based Gate Stacks", Electron Devices Meeting, 2005, IEDM Technical Digest, IEEE International: pg. 609-612, December.
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Ungersboeck, E.; Kosina, H. (2005), "The Effect of Degeneracy on Electron Transport in Strained Silicon Inversion Layers", Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on: pg. 311-314, Tokyo, Japan, September.
Ceric, H.; Karner, M.; Nentchev, A.; Schwaha, P.; Ungersboeck, E.; Selberherr, S. (2005), "Vista Status Report", institute for Microelectronics, Technical University Vienna.
Shi, X.; Wong, M. (2005), "Effects of substrate doping on the linearly extrapolated threshold voltage of symmetrical DG MOS devices", IEEE Transactions on Electron Devices, 52, 7, July.
Aberg, I.; Hoyt, J.L. (2005), "Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm", IEEE Electron Device Letters, 26, 9.
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Tang, T.W.; O'Regan, T.; Wu, B. (2004), "Thomas-Fermi Approximation for a Two-Dimensional Electron Gas at Low Temperatures", Journal of Applied Physics, 95, 12: pg. 71-73, June.
Choi, Y.K. (2004), "FinFET for Terabit Era", Journal of Semiconductor Technolgoy and Science, 4, 1, March.
Khakifrooz, A.; Nayfeh, O. M.; Antoniadis, D. A. (2004), "Assessing the Performance Limits of Ultra-Thin Double-Gate MOSFETs: Silicon vs. Germanium", SOI Conference, 2004, Proceedings. 2004 IEEE International: pg. 79-80, October.
Trivedi, V.P.; Fossum, J. G.; Gamiz, F. (2004), "A Compact QM-Based Mobility Model for Nanoscale Ultra-Thin-Body CMOS Devices", Electron Devices Meeting, 2004, IEDM Technical Digest, IEEE International: pg. 763-766, December. 0-7803-8684-1. (DOI: 10.1109/IEDM.2004.1419284).
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Affiliated authors
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Alam, M.K.; Alam, A.; Ahmed, S.; Rabbani, M.G.; Khosru, Q.D.M. (2007), "Wavefunction Penetration Effect on C-V Characteristic of Double Gate MOSFET", Semiconductor Device Research Symposium, 2007 International: pg. 1-2, December.
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Mukhopadhyay, S.; Kim, K.; Kim, J.; Lo, H.-H.; Joshi, R.; Chuang, C.-T.; Roy, K. (2007), "Estimation of Gate-to-Channel Tunneling Current in Ultra-Thin Oxide sub-50 nm Double Gate Devices", Microelectronics Hournal, 38, 8-9: pg. 931-941, September.
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Ahmed, S.; Klimeck, G.; Kearney, D.; McLennan, M.; Anantram, M.P. (2007), "Quantum Simulations of Dual Gate MOSFET Devices: Building and Deploying Community Nanotechnology Software Tools on nanoHUB.org", International Journal of High Speed Electronics and Systems, 17, 3: pg. 485-494, September.
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Lundstrom, M.S.; Cantley, K.D.; Pal, H.S. (2007), "Nanoscale Transistors: Physics and Materials", The Materials Research Society: The Materials Gateway, 958.
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Mukhopadhyay, S.; Kim, K.; Chuang, C.T.; Roy, K. (2006), "Modeling and Analysis of Leakage Currents in Double-Gate Technologies", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transaction on, 25, 10: pg. 2052-2061, October.
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Mukhopadhyay, S.; Kim, K.; Kim, J.-J.; Lo, S.-H.; Joshi, R.V.; Chuang, C.-T.; Roy, K. (2005), "Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits.", Sixth International Symposium on Quality of Electronic Design, 2005. ISQED 2005.
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Mukhopadhyay, S.; Kim, K.; Chuang, C.-T.; Roy, K. (2005), "Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits", The 2005 International Symposium on Low Power Electronics and Design: pg. 8-13. 1-59593-137-6. (DOI: 10.1145/1077603.1077608).
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Ren, Z.; Hegde, S.; Doris, B.; Oldiges, P.; Kanarsky, T.; Dokumaci, O.; Roy, R.; Leong, M.; Jones, E.C.; Wong, H.-S.P. (2002), "An Experimental Study on Transport Issues and Electrostatics of Ultrathin Body SOI pMOSFETs", Electron Device Letters, IEEE, 23, 10: pg. 609-611, October. 1558-0563. (DOI: 10.1109/LED.2002.803757).
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Rumsey, D. (2001), "Electrical Characterization of Bulk MOSFETs in Terms of Backscattering Coefficients" (Master's Thesis), Purdue University, December.
Reviews
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Posted on 13 January, 2007 by Anonymous
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Posted on 15 October, 2006 by Anonymous
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Posted on 22 April, 2006 by Jeon, Kanghoon
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Posted on 17 January, 2006 by denis mamaluy
It is very nice that Schred gives a possibility to compare semiclassical and quantum simulations.
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