NanoWire
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Usage Stats Last 12 Months: Updated 22 May, 2008 more › Users: 474 Jobs: 7534 Avg. exec. time: 11 hours Reviews & Citations Google/IEEE: updated 08 Feb, 2008 Avg. Review: Citations: 2
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| Contributor(s) | Jing Wang Purdue University, West Lafayette Eric Polizzi University of Massachusetts, Amherst Clemens Heitzinger, Gerhard Klimeck, Saumitra Raj Mehrotra, Ben Haley Purdue University, West Lafayette |
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| At a glance | Simulate electron transport in 3D through nanowires in the effective mass approximation subject to 3D Poisson solution |
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| Description | Silicon nanowire transistors are promising device structures for future integrated circuits. Short channel effects are becoming more and more important in the nanoscale regime, and therefore effective gate control will be necessary to achieve good device performance. In contrast to planar MOSFETs which have uniform charge and potential profiles in the transverse direction (i.e., normal to both the gate and the source-drain direction), a silicon nanowire transistor has a genuinely 3D distribution of electron density and electrostatic The mode space approach treats quantum confinement and transport separately. The simulations you can perform consist of the following steps:
In summary you can use three transport models:
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| Credits | This tool is based on the work of Jing Wang, Eric Polizzi, and Clemens Heitzinger. |
| Cite this work | If you reference this work in a publication, please cite as follows:
In addition, we would appreciate it if you would add the following acknowledgment to your publication:
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| Version released | 08 May, 2008 |
| Type | Tools |
| Tags |
Citations
The following are publications that have cited this resource, separated by their affiliation to the NCN.
Non-affiliated authors
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Mehrotra, S.; Roenker, K.P. (2007), "Process Variation Study for Silicon Nanowire Transistors", Microelectronics and Electron Devices, 2007 IEEE Workshop on: pg. 40--41, 04.
Affiliated authors
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Klimeck, G.; Ahmed, SS.; Kharche, N.; Korkusinski, M.; Usman, M.; Prada, M.; Boykin, T.B. (2007), "Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D - Partt II: Applications", Electron Devices, IEEE Transactions on, 54, 9: pg. 2090-2099, 09. 0018-9383.
Mehrotra, S.; Roenker, K.P. (2007), "Process Variation Study for Silicon Nanowire Transistors", Microelectronics and Electron Devices, 2007 IEEE Workshop on: pg. 40--41, 04.
Affiliated authors
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Klimeck, G.; Ahmed, SS.; Kharche, N.; Korkusinski, M.; Usman, M.; Prada, M.; Boykin, T.B. (2007), "Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D - Partt II: Applications", Electron Devices, IEEE Transactions on, 54, 9: pg. 2090-2099, 09. 0018-9383.
Reviews
The following are reviews of this resource from other site members.
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Posted on 18 September, 2007 by Osama Munir Nayfeh
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Posted on 16 June, 2007 by Saumitra Raj Mehrotra
I have been using nanowire for research as a part of my Masters thesis. Working with this tool has been a great experience with new insights into working of nanoscaled FETs. Comparison with experimental results was pretty close which gave an impetus to carry forward the research. Eg. Variation of threshold voltage with diameter ~5nm predicted by nanowire to be 33-49mV/nm is near to the experimentally reported result of 35 mV/nm by N. Singh et al at IEDM, Dec 2006. Also various optimization and comparative studies provided interesting results. One of the works led to conference paper -"Process Variation Study for Silicon Nanowire Transistors" presented at WMED, Boise, April 2007. I acknowledge the huge computational load managed and the user-friendly interface maintained by the nanohub team.
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Posted on 26 May, 2006 by Jing Wang
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Posted on 20 May, 2006 by Petrica Cristea
Related Questions & Answers
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