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NanoWire

This resource has a 9.9 Ranking

Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›

Usage Stats
Last 12 Months: Updated 22 May, 2008 more ›
Users: 474
Jobs: 7534
Avg. exec. time: 11 hours
Reviews & Citations
Google/IEEE: updated 08 Feb, 2008
Avg. Review: 5.0 out of 5 stars
Citations: 2

4 reviews (Review this)

2 citations

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Contributor(s) Jing Wang
Purdue University, West Lafayette

Eric Polizzi
University of Massachusetts, Amherst

Clemens Heitzinger, Gerhard Klimeck, Saumitra Raj Mehrotra, Ben Haley
Purdue University, West Lafayette
At a glance Simulate electron transport in 3D through nanowires in the effective mass approximation subject to 3D Poisson solution
Screenshots
  • Screenshot #1
  • Screenshot #2
Description

Silicon nanowire transistors are promising device structures for future integrated circuits. Short channel effects are becoming more and more important in the nanoscale regime, and therefore effective gate control will be necessary to achieve good device performance.
Devices based on silicon nanowires can be manufactured with multigate and gate-all-around transistors and you can explore them with this tool.

In contrast to planar MOSFETs which have uniform charge and potential profiles in the transverse direction (i.e., normal to both the gate and the source-drain direction), a silicon nanowire transistor has a genuinely 3D distribution of electron density and electrostatic
potential. Therefore self-consistent 3D simulations are mandatory, and you run them with this tool. One of the transport models assumes ballistic transport, which gives the upper performance limit of the devices. The effective-mass mode space approach (either coupled or uncoupled) produces high computational efficiency that makes this
simulator practical for extensive device simulation and
design. Scattering is treated by so-called Büttiker probes, which was previously used in metal-oxide-semiconductor field effect transistor simulations. The effects of scattering on both internal device
characteristics and terminal currents can be examined, which enables our simulator to be used for the exploration of realistic performance limits of silicon-nanowire transistors.

The mode space approach treats quantum confinement and transport separately. The simulations you can perform consist of the following steps:

  1. Solve the 3D Poisson equation for the electrostatic potential.
  2. Solve the 2D Schrödinger equation with closed boundary conditions for each cross section (or slice) of the nanowire transistor to obtain the electron subbands (along the nanowire) and eigenfunctions.
  3. Solve the coupled or uncoupled nonequilibrium Green function (NEGF) transport equations for the electron charge density.
  4. Go to step (1) to calculate the electrostatic potential. If the self-consistent loop has converged, calculate the electron current using the NEGF approach and show the results.

In summary you can use three transport models:

  1. Uncoupled mode space with averaging of the potential on the slices. This is the fastest option.
  2. Uncoupled mode space with scattering by Büttiker probes and no averaging of the potential. This option takes much more time.
  3. Coupled mode space without scattering and without averaging of the potential. Due to the coupling of the modes, this option is also much slower than the first one. But no worries; you can start the simulation and login back later to check the results.

Credits

This tool is based on the work of Jing Wang, Eric Polizzi, and Clemens Heitzinger.

Cite this work

If you reference this work in a publication, please cite as follows:

  • Jing Wang, Eric Polizzi, Mark Lundstrom, "A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation," Journal of Applied Physics 96(4), pages 2192-2203, 2004.
  • Wang, Jing; Polizzi, Eric; Heitzinger, Clemens; Klimeck, Gerhard; Mehrotra, Saumitra Raj; Haley, Ben (2006), "NanoWire", http://www.nanohub.org/tools/nanowire/, accessed on 2008-05-22 16:08:57.

    BibTex | EndNote

In addition, we would appreciate it if you would add the following acknowledgment to your publication:

  • Simulation services for results presented here were provided by the Network for Computational Nanotechnology (NCN) at nanoHUB.org

Version released 08 May, 2008
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Reviews

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  1. 5.0 out of 5 stars 

    Posted on 18 September, 2007 by Osama Munir Nayfeh

  2. 5.0 out of 5 stars 

    Posted on 16 June, 2007 by Saumitra Raj Mehrotra

    I have been using nanowire for research as a part of my Masters thesis. Working with this tool has been a great experience with new insights into working of nanoscaled FETs. Comparison with experimental results was pretty close which gave an impetus to carry forward the research. Eg. Variation of threshold voltage with diameter ~5nm predicted by nanowire to be 33-49mV/nm is near to the experimentally reported result of 35 mV/nm by N. Singh et al at IEDM, Dec 2006. Also various optimization and comparative studies provided interesting results. One of the works led to conference paper -"Process Variation Study for Silicon Nanowire Transistors" presented at WMED, Boise, April 2007. I acknowledge the huge computational load managed and the user-friendly interface maintained by the nanohub team.

  3. 5.0 out of 5 stars 

    Posted on 26 May, 2006 by Jing Wang

  4. 5.0 out of 5 stars 

    Posted on 20 May, 2006 by Petrica Cristea

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