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A new generation of Predictive Technology Models (PTM) is developed for 130nm to 32nm technology nodes. These predictive model files are compatible with standard circuit simulators, such as SPICE, and scalable with a wide range of process variations. With PTM, competitive circuit design and research can start even before the advanced semiconductor technology is fully developed. As compared to previous Berkeley Predictive Technology Model (BPTM), the new predictive methodology has better physicality and scalability over a wide range of process and design conditions. Both nominal values and process sensitivity are captured in the new PTM for robust design research. Excellent predictions have been verified from 250nm to 45nm nodes. The importance of physical correlations among parameters and the impact of process variations have been evaluated. Model files for bulk CMOS with Leff as low as 13nm are available here.

This work was funded by the Center for Circuit & System Solutions (C2S2) and the Materials, Stuctures and Device Focus Center (MSD).

• Wei Zhao and Yu Cao, TED, vol. 53, no. 11, pp. 2816-2823, 2006.
• http://www.eas.asu.edu/~ptm

If you reference this work in a publication, please cite as follows:

• Wei Zhao and Yu Cao, TED, vol. 53, no. 11, pp. 2816-2823, 2006.

• Zhao, Wei; Cao, Yu (2007), "Nano-CMOS," doi: 10254/nanohub-r2327.4.

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• Simulation services for results presented here were provided by the Network for Computational Nanotechnology (NCN) at nanoHUB.org

1. characterization
2. circuits
3. microelectronics
4. nano-transistors
5. nanoelectronics