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A Phase-Changing Oxide for PS Silicon Photonics
Online Presentations | 03 Nov 2016 | Contributor(s):: Richard Haglund
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Abdurrahman Javid Shaikh
I am currently working towards my PhD at Collaborative µElectronic Design Excellence Centre (CEDEC), University Sains Malaysia (USM). My areas of interests include Theoretical and Computational...
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Aditi Singh
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Advanced CMOS Device Physics for 7 nm and Beyond
Presentation Materials | 16 Dec 2015 | Contributor(s):: Scott Thompson
This presentation is part of 2015 IEDM tutorials The industry march along Moore's Law continues and new semiconductor nodes at 7 and beyond will certainly happen. However, many device, material, and economical challenges remain. This tutorial will target understanding key device concepts for...
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Akash Paharia
Currently, I am an undergraduate student in Electrical Department of Indian Institute of Technology ,Delhi. I am interested in knowing about new technologies in the field of semiconductors device...
https://nanohub.org/members/38550
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Arijit Sengupta
A motivated individual with an aptitude in leading and managing teams for projects and related work. My goal is to become associated with a company or an university where I can utilize my skills to...
https://nanohub.org/members/209943
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Carbon-Based Nanoswitch Logic
Online Presentations | 28 Mar 2013 | Contributor(s):: Stephen A. Campbell
This talk discusses a rather surprising possibility: the use of carbon-based materials such as carbon nanotubes and grapheneto make nanomechanical switches with at least an order of magnitude lower power dissipation than the low power CMOS options and performance between the various CMOS...
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Charles Augustine
Charles Augustine (S’08-M’11) received the Bachelors in Electronics from BITS, Pilani, India in 2004 and the PhD degree in Electrical and Computer Engineering from Purdue University in...
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CMOS+X: Integrated Ferroelectric Devices for Energy Efficient Electronics
Online Presentations | 09 Dec 2022 | Contributor(s):: Sayeef Salahuddin
In this talk, I shall briefly present how integrated ferroelectric devices offer a new pathway in this context. First, I shall discuss the phenomenon of negative capacitance in ferroelectric materials. A fundamentally new state in the ferroelectrics, negative capacitance promises to reduce...
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Computational and Experimental Study of Transport in Advanced Silicon Devices
Papers | 28 Jun 2013 | Contributor(s):: Farzin Assad
In this thesis, we study electron transport in advanced silicon devices by focusing on the two most important classes of devices: the bipolar junction transistor (BJT) and the MOSFET. In regards to the BJT, we will compare and assess the solutions of a physically detailed microscopic model to...
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Computational Electronics
Courses | 02 Jun 2006 | Contributor(s):: Dragica Vasileska
Scaling of CMOS devices into the nanometer regime leads to increased processing cost. In this regard, the field of Computational Electronics is becoming more and more important because device simulation offers unique possibility to test hypothetical devices which have not been fabricated yet...
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Course on Beyond CMOS Computing
Teaching Materials | 06 Jun 2013 | Contributor(s):: Dmitri Nikonov
Complementary metal-oxide-semiconductor (CMOS) field effect transistors (FET) underpinned the development of electronics and information technology for the last 30 years. In an amazing saga of development, the semiconductor industry (with a leading role of Intel) has shrunk the size of these...
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Design and Compact Modeling of CMOS-MEMS Resonant Body Transistors
Online Presentations | 06 Jun 2014 | Contributor(s):: Dana Weinstein, Luca Daniel, Bichoy W. Bahr
This talk presents the latest results of the CMOS Resonant Body Transistor (RBT) fabricated in standard 32nm SOI CMOS. Using phononic crystals formed from the CMOS stack, we will discuss methods for 10x improvement of Q and suppression of spurious modes.
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Device Options and Trade-offs for 5 nm CMOS Technology Seminar Series
Series | 30 Sep 2015 | Contributor(s):: Mark Lundstrom
Today's CMOS technology is so-called 14-nm technology. 10 nm technology development is well underway, and 7 nm has begun. It will soon be time to select a technology for the 5 nm node. To help understand the device options, what each on promises, what the challenges and trade-offs are,...
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ECE 612 Lecture 18A: CMOS Process Steps
Online Presentations | 12 Nov 2008 | Contributor(s):: Mark Lundstrom
Outline: 1) Unit Process Operations,2) Process Variations.
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ECE 612 Lecture 18B: CMOS Process Flow
Online Presentations | 18 Nov 2008 | Contributor(s):: Mark Lundstrom
For a basic, CMOS process flow for an STI (shallow trench isolation process), see: http://www.rit.edu/~lffeee/AdvCmos2003.pdf.This lecture is a condensed version of the more complete presentation (listed above) by Dr. Fuller.
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ECE 612 Lecture 22: CMOS Circuit Essentials
Online Presentations | 24 Nov 2008 | Contributor(s):: Mark Lundstrom
Outline: 1) The CMOS inverter,2) Speed,3) Power,4) Circuit performance,5) Metrics,6) Limits.This lecture is an overview of CMOS circuits. For a more detailed presentation, the following lectures from the Fall 2006 teaching of this course should be viewed:Lecture 24: CMOS Circuits, Part I (Fall...
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ECE 612 Lecture 23: RF CMOS
Online Presentations | 02 Dec 2008 | Contributor(s):: Mark Lundstrom
Outline: 1) Introduction,2) Small signal model,3) Transconductance,4) Self-gain,5) Gain bandwidth product,6) Unity power gain,7) Noise, mismatch, linearity…,8) Examples
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Emerging CMOS Technology at 5 nm and Beyond: Device Options and Trade-offs
Presentation Materials | 14 Dec 2015 | Contributor(s):: Mark Lundstrom, Xingshu Sun, Dimitri Antoniadis, Shaloo Rakheja
Device Options and Trade-offs
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Eric Sanchez
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