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New Dimension in Performance: Harnessing 3D Integration Technology

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Contributor(s) Kerry Bernstein
IBM T.J. Watson Research Center
Abstract Despite generation on generation of scaling, computer chips have remained essentially 2-dimensional. Improvements in on-chip wire delay, and in the total number of inputs and outputs has not been able to keep up with improvements to the transistor, and its getting harder and harder to hide it! 3D chip technologies come in a number of flavors, but are receiving lots of attention lately as a means of extending CMOS performance. Designing for three dimensions, however, forces us to look at formerly-two-dimensional integration issues quite differently. IBM as well as other companies and research institutions are developing ways of addressing these challenges. This talk will introduce major 3D concepts and IBM’s approach. A 3D “fly-through” movie of an actual IBM 3D design will be shown.
Biography Kerry Bernstein Kerry Bernstein is a Senior Technical Staff Member at the IBM T.J. Watson Research Center, Yorktown Hts., NY. He is currently Principal Investigator of IBM’s 3D Integration Program. Mr. Bernstein received the B.S degree in electrical engineering degree from Washington University in St. Louis, and joined IBM in 1978. He holds 50 US Patents, and is a co-author of 3 college textbooks and multiple papers on high speed CMOS. His interests are in the area of high performance / low power advanced circuits and technologies. Mr. Bernstein is an IEEE Fellow.
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  • Bernstein, Kerry (2007), "New Dimension in Performance: Harnessing 3D Integration Technology," http://www.nanohub.org/resources/3596/.

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Date posted 29 Nov, 2007
Time 02:30 PM, October 04, 2007
Location Knoy B033, Purdue University, West Lafayette, IN
Type Online Presentations
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