Device Physics and Simulation of Silicon Nanowire Transistors
- This resource has a 9.9 Ranking
-
Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›
Usage Stats Last 12 Months: updated 01 May, 2008 Users: 222 Reviews & Citations Google/IEEE Avg. Review: Citations: 0
Download (PDF, 2.73 Mb)
| Contributor(s) | Jing Wang Purdue University, West Lafayette |
|---|---|
| Abstract | As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention from both the semiconductor industry and academia. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this thesis are:
The results show that SNWTs provide better scaling capability than planar MOSFETs. A microscopic, quantum treatment of surface roughness scattering (SRS) in SNWTs has also been accomplished, and it shows that SRS is less important in SNWTs with small diameters than in planar MOSFETs. Finally, bandstructure effects in SNWTs with small diameters have been examined by using an empirical tight binding model, and a channel orientation optimization has been done for both silicon and germanium nanowire field-effect transistors. |
| Credits | PhD thesis for Jing Wang, funded by the Semiconductor Research Corporation (SRC), the MARCO focus center on Materials, Structures and Devices (MSD), and the NSF Network for Computational Nanotechnology (NCN). |
| Cite this work | If you reference this work in a publication, please cite as follows:
|
| Date posted | 20 May, 2006 |
| Type | Publications |
| Tags |
Citations
The following are publications that have cited this resource, separated by their affiliation to the NCN.
No citations found.
Reviews
The following are reviews of this resource from other site members.
No reviews found. Be the first to review this resource!
Related Resources
The following are resources that may cover similar or related topics.
-
10.0 Ranking Tools
Bandstructure Lab
Bandstructure Lab
Type Tools Contributor(s) Mathieu Luisier, Raseong Kim, Neophytos Neophytou, Michael McLennan, Jing Wang, Anisur Rahman, Gerhard Klimeck, Mark Lundstrom Date 19 May, 2006 Avg. Rating (3) Rate this Simulate electronic band structure for a variety of bulk materials and device geometries such as quantum wells and nanowires.
-
9.7 Ranking Online Presentations
Bandstructure in Nanoelectronics
Bandstructure in Nanoelectronics
Type Online Presentations Contributor(s) Gerhard Klimeck Date 01 Nov, 2005 Avg. Rating (5) Rate this Electrical Engineering curricula typically only touch the bandstructure of solids early in the introduction of solid state devices. Critical parameters such as bandedges, effective masses and degeneracies are extracted from the bandstructure and the atomistic details of the origin of the abstract …
- 10.0 Ranking Online Presentations ECE 453 Lecture 16: Bandstructure 1
- 10.0 Ranking Online Presentations ECE 453 Lecture 17: Bandstructure 2
- 9.7 Ranking Online Presentations ECE 453 Lecture 18: Bandstructure 3
- 9.9 Ranking Online Presentations ECE 453 Lecture 19: Bandstructure 4
-
9.4 Ranking Courses
Quantum Transport: Atom to Transistor
Quantum Transport: Atom to Transistor
Type Courses Contributor(s) Supriyo Datta Date 07 Aug, 2006 Avg. Rating (21) Rate this The development of "nanotechnology" has made it possible to engineer materials and devices on a length scale as small as several nanometers (atomic distances are ~ 0.1 nm). The properties of such "nanostructures" cannot be described in terms of macroscopic parameters like mobility and diffusion …
-
9.1 Ranking Publications
Exploring New Channel Materials for Nanoscale CMOS
Exploring New Channel Materials for Nanoscale CMOS
Type Publications Contributor(s) Anisur Rahman Date 21 May, 2006 Avg. Rating (2) Rate this The improved transport properties of new channel materials, such as Ge and III-V semiconductors, along with new device designs, such as dual gate, tri gate or FinFETs, are expected to enhance the performance of nanoscale CMOS devices. Novel process techniques, such as ALD, high-k dielectrics, and …