Nanowire
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Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›
Usage Stats Overall Period: Updated 14 Oct, 2008 Users: 1195 Jobs: 17891 Avg. exec. time: 3 hours Reviews & Citations Google/IEEE: updated 03 Jun, 2008 Avg. Review: Citations: 7
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Available Versions
- 2.02 (published)
- 2.0.1 (unpublished)
- 2.0 (unpublished)
- 1.0 (unpublished)
| Version | 2.02 - published on 25 Sep, 2008 |
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| Contributor(s) | Eric Polizzi University of Massachusetts, Amherst Clemens Heitzinger, Gerhard Klimeck, Saumitra Raj Mehrotra, Ben Haley Purdue University, West Lafayette |
| At a glance | Simulate 3D nanowire transport in the effective mass approximation and 3D Poisson solution |
| Screenshots | |
| Description | Silicon nanowire transistors are promising device structures for future integrated circuits. Short channel effects are becoming more and more important in the nanoscale regime, and therefore effective gate control will be necessary to achieve good device performance. Devices based on silicon nanowires can be manufactured with multigate and gate-all-around transistors and you can explore them with this tool. In contrast to planar MOSFETs which have uniform charge and potential profiles in the transverse direction (i.e., normal to both the gate and the source-drain direction), a silicon nanowire transistor has a genuinely 3D distribution of electron density and electrostatic potential. Therefore self-consistent 3D simulations are mandatory, and you run them with this tool. One of the transport models assumes ballistic transport, which gives the upper performance limit of the devices. The effective-mass mode space approach (either coupled or uncoupled) produces high computational efficiency that makes this simulator practical for extensive device simulation and design. Scattering is treated by so-called Büttiker probes, which was previously used in metal-oxide-semiconductor field effect transistor simulations. The effects of scattering on both internal device characteristics and terminal currents can be examined, which enables our simulator to be used for the exploration of realistic performance limits of silicon-nanowire transistors. The mode space approach treats quantum confinement and transport separately. The simulations you can perform consist of the following steps:
In summary you can use three transport models:
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| Credits | This tool is based on the work of Jing Wang, Eric Polizzi, and Clemens Heitzinger. |
| Cite this work | If you reference this work in a publication, please cite as follows:
In addition, we would appreciate it if you would add the following acknowledgment to your publication:
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| Type | Tools |
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Citations
The following are publications that have cited this resource, separated by their affiliation to the NCN.
Non-affiliated authors
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Mehrotra, S.R.; Roenker, K.P. (2007), "Process Variation Study for Silicon Nanowire Transistors," Microelectronics and Electron Devices, 2007 IEEE Workshop on: pg. 40--41, 04.
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Mehrotra, S.R.; Roenker, K.P. (2007), "A Simulation Study of Silicon Nanowire Field Effect Transistors (FETs)" (Master's Thesis), University of Cincinnati, 02.
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Myers-Riggs, R.R.; Roenker, K.P. (2005), "Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport" (Master's Thesis), University of Cincinnati.
Affiliated authors
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Klimeck, G.; Ahmed, S.S.; Kharche, N.; Korkusinski, M.; Usman, M.; Prada, M.; Boykin, T.B. (2007), "Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D - Partt II: Applications," Electron Devices, IEEE Transactions on, 54, 9: pg. 2090-2099, 09. 0018-9383.
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McLennan, M.; Kennell, R.; Ebert, D.S.; Klimeck, G.; Qiao, W. (2006), "Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications," IEEE Transactions on Visualization and Computer Graphics, 12, 5: pg. 1061-1068. 1077-2626. (DOI: 10.1109/TVCG.2006.150).
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Wang, J.; Lundstrom, M.S. (2005), "Device Physics and Simulation of Silicon Nanowire Transistors" (PhD Thesis), Purdue University, 08.
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Wang, J.; Polizzi, E.; Lundstrom, M.S. (2003), "A computational study of ballistic silicon nanowire transistors," Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International: pg. 29.5.1-29.5.4, 12. 0-7803-7872-5. (DOI: 10.1109/IEDM.2003.1269375).
Mehrotra, S.R.; Roenker, K.P. (2007), "Process Variation Study for Silicon Nanowire Transistors," Microelectronics and Electron Devices, 2007 IEEE Workshop on: pg. 40--41, 04.
Mehrotra, S.R.; Roenker, K.P. (2007), "A Simulation Study of Silicon Nanowire Field Effect Transistors (FETs)" (Master's Thesis), University of Cincinnati, 02.
Myers-Riggs, R.R.; Roenker, K.P. (2005), "Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport" (Master's Thesis), University of Cincinnati.
Affiliated authors
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Klimeck, G.; Ahmed, S.S.; Kharche, N.; Korkusinski, M.; Usman, M.; Prada, M.; Boykin, T.B. (2007), "Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D - Partt II: Applications," Electron Devices, IEEE Transactions on, 54, 9: pg. 2090-2099, 09. 0018-9383.
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McLennan, M.; Kennell, R.; Ebert, D.S.; Klimeck, G.; Qiao, W. (2006), "Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications," IEEE Transactions on Visualization and Computer Graphics, 12, 5: pg. 1061-1068. 1077-2626. (DOI: 10.1109/TVCG.2006.150).
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Wang, J.; Lundstrom, M.S. (2005), "Device Physics and Simulation of Silicon Nanowire Transistors" (PhD Thesis), Purdue University, 08.
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Wang, J.; Polizzi, E.; Lundstrom, M.S. (2003), "A computational study of ballistic silicon nanowire transistors," Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International: pg. 29.5.1-29.5.4, 12. 0-7803-7872-5. (DOI: 10.1109/IEDM.2003.1269375).
Reviews
The following are reviews of this resource from other site members.
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Posted on 18 September, 2007 by Osama Munir Nayfeh
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Posted on 16 June, 2007 by Saumitra Raj Mehrotra
0 0 Login to vote I have been using nanowire for research as a part of my Masters thesis. Working with this tool has been a great experience with new insights into working of nanoscaled FETs. Comparison with experimental results was pretty close which gave an impetus to carry forward the research. Eg. Variation of threshold voltage with diameter ~5nm predicted by nanowire to be 33-49mV/nm is near to the experimentally reported result of 35 mV/nm by N. Singh et al at IEDM, Dec 2006. Also various optimization and comparative studies provided interesting results. One of the works led to conference paper -"Process Variation Study for Silicon Nanowire Transistors" presented at WMED, Boise, April 2007. I acknowledge the huge computational load managed and the user-friendly interface maintained by the nanohub team.
reply | report abuse -
Posted on 26 May, 2006 by Jing Wang
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Posted on 20 May, 2006 by Petrica Cristea
See also
The following are resources that may cover similar or related topics.
- 0.0 Ranking Topic The NEGF Approach to Nano-Device Simulation
Related Questions & Answers
The following are questions related to this tool that were posted by other users in our questions and answers forum.
- Problem during simulation - 1 response
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