JFETIDG model
=============

This directory contains the files, QA test specifications,
QA reference results, and documentation for the JFETIDG model.
The Verilog-A files listed below include an identifier
that is added before the ".va" extension. This identifier
follows the recommended best practices and NEEDS/CMC
requirement, and is of the form _vV_S_R[_A] where V is the
major version number, S is the subversion number, R is the
revision number, and A is an optional test release identifier
(a/b/... for alpha/beta/...) that is removed for an official
release after testing is complete.

jfetidg.va           is the top-level Verilog-A file for JFETIDG
jfetidgIds.va        contains analog functions for the core
                     Vdsat and Ids calculations for JFETIDG
general.va           general macros and constant definitions
junction.va          PN-junction model building blocks, mostly
                     analog functions, with one macro
simulatorFlags.va    flags that need to be set to work around
                     the limitations of some Verilog-A compilers
qaJfetidg            specifications of a comprehensive set
                     of QA tests for all aspects of JFETIDG:
                     Ids, with all possible combinations of
                     depletion-pinching, velocity saturation,
                     and self-heating being turned on or off;
                     CLM and DIBL; parasitic pn-junction currents
                     (including breakdown), pn-junction
                     capacitances (including diffusion
                     components), and fixed capacitances;
                     noise; geometry scaling.
qaJfetidgTemp        specification for QA tests for temperature
                     mappings (both TC1/TC2 and TSL/TSH)
reference/           directory with reference results for
                     each QA test
doc/                 directory with documentation, click
                     on the file doc/index.html which
                     should launch your default web browser
                     and display the documentation;
                     click on each section heading
                     to expand/un-expand each section

The core model calculation in jfetidgIds.va are separated
from the non-core calculations in jfetidg.va to make the code
easer to comprehend. The structure of the model code
can be understood by looking into jfetidg.va, which contains
parameter definitions, geometry mappings, temperature mappings,
and all extrinsic element calculations, uncluttered by
the core physics-based model calculations. Conversely,
the core physics-based calculations can be reviewed
by looking at the code in jfetidgIds.va, without being obscured
by extraneous details of the non-core calculations in jfetidg.va.

v1.0.3 updates
==============

July 14, 2017

1. Fixed bug in finite doping source width model

v1.0.2 updates
==============

June 07, 2017

1. The TC1/TC2 temperature model turns out to be inaccurate
   over a wide temperature range, e.g. where self-heating
   is very significant. Included alternative temperature
   models for the core JFET zero-bias resistance that
   are more accurate over a wide temperature range.
2. The thermal conductivity temperature exponent range
   was changed to allow positive values.

v1.0.1 updates
==============

May 25, 2017

1. The file simulatorFlags.vams was renamed simulatorFlags.va
   (one compiler did not like the .vams extension).
2. The jfetidgIdsat analog function was updated so that the core Ids
   is returned via the function name (the LRM did not show this in
   the example for returning more than one output, but one compiler
   complained about there not being an output that matched the
   analog function name), not via an additional argument. This removed
   the need for the "dummy" variable in the main model code.
   Vsp and Vdsat are also returned as outputs, and added as operating
   point information.
3. The "hidden state" issues detected by VALint have been fixed, by
   having all such variables assigned to outside of conditional blocks.
4. Capacitances added to operating point output, and updated how the
   operating point parameter "v" is determined.
5. exp() was replaced by limexp() where allowable.
6. In the "general" macros the arguments of CLAMP macro were changed
   to lo/hi avoid conflict with the Verilog-A min/max function names,
   and the niPsp_m3 macro was updated to clip tK to 873.15, to
   simplify usage.

v1.0.0 release
==============

March 22, 2017