********************************************************************
* Transition Metal Dichalcogenide Field Effect Transistors 
*             Verilog-A Model (MoS2)
*		Test Circuit
*   
*   Morteza Gholipour, Babol University of Technology, Iran
*   Deming Chen, University of Illinois at Urbana Champaign
*   
*   File name: tmdfet_sample.sp
*   
********************************************************************

***************************************************
*
* Sample HSPICE Deck
*
***************************************************

.TITLE 'IDS vs VGS for TMDFET'


***************************************************
.options POST 
.options AUTOSTOP
.options INGOLD=4
.options NUMDGT=4
.param   TEMP=27
***************************************************


***************************************************
* Include relevant model files
***************************************************
.hdl "tmdfetn_v_1_0_0.va"	"tmdfetp_v_1_0_0.va"
***************************************************

* Supplies and params:
.param SUPPLY=0.5 
.param strain=0	

***********************************************************************
* Define power supply
***********************************************************************
Vdd	Drain	GND 	DC	SUPPLY
Vss	Source	GND 	DC	0
Vgg	Gate	0	0.3

*Vddp	Drainp	GND	DC	SUPPLY
*Vggp	Gatep	Drainp	0.55

***********************************************************************
* Main Circuits
***********************************************************************
* n type TMDFET
XTMDn Drain Gate Source Gate tmdfetnmos strain=strain

* p type TMDFET
*XTMDp Drainp Gatep Source Drainp tmdfetpmos strain=strain


***********************************************************************
* Measurements
***********************************************************************
* test n-type TMDFET, Ids vs. Vgs
.DC	Vgg	start=-1	stop=1	step=0.01
+ SWEEP 	strain	poi 3 0 2 10

* test p-type TMDFET, Ids vs. Vgs
*.DC	Vggp	start=-1	stop=1	step=0.01
*+ SWEEP	SUPPLY	0.2 0.6 0.1

.end