Magnetic Tunnel Junction (MTJ) as Stochastic Neurons and Synapses: Stochastic Binary Neural Networks, Bayesian Inferencing, Optimization Problems
Online Presentations | 26 Oct 2018 | Contributor(s): Abhronil Sengupta, Kaushik Roy
In this presentation, we provide a multi-disciplinary perspective across the stack of devices, circuits, and algorithms to illustrate how the stochastic switching dynamics of spintronic devices in the presence of thermal noise can provide a direct mapping to the units of such computing...
Re-Engineering Computing For Next Generation Autonomous Intelligent Systems: Devices, Circuits, and Algorithms
Online Presentations | 27 Aug 2018 | Contributor(s): Kaushik Roy, Abhronil Sengupta
Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional "von-Neumann"...
Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance
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Online Presentations | 28 Nov 2006 | Contributor(s): Kaushik Roy
The scaling of technology has produced exponential growth in transistor development and computing power in the last few decades, but scaling still presents several challenges. These two lectures will cover device aware CMOS design to address power, reliability, and process variations in scaled...
Design in the Nanometer Regime: Process Variation
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Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems — severe short channel effects, exponential increase in...