nanoHUB-U Fundamentals of Nanotransistors/Lecture 2.9: Unit 2 Summary
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[Slide 1] So welcome back. We are ready to wrap up Unit 2. 

[Slide 2] We've covered a lot of ground in Unit 2. What I'd like to do in this lecture is just go over the key concepts, the things that you should take away from this material that we've discussed in Unit 2. 

[Slide 3] So remember, our focus is on the charge. In Units 3 and 4, our emphasis is going to be on velocity or how that charge moves across the channel. So we began in the first lecture by talking about some basic concepts about MOS capacitors and how bands bend that we do band diagrams like this. And we pointed out that we're going to consider that the bulk of the semiconductor is grounded. That's our reference for zero potential. That's just an arbitrary reference, but it's a convenient for-- one for us. We remember that a positive potential lowers electron energy. So whenever we see the electron conduction band going down or the valence band going down, we know that the electrostatic potential is increasing. We can easily determine the electrostatic potential at any location. It is simply the Q times the amount that the energy has dropped by. So that's how electrostatic potential and energy bands are related. They're really very much the same thing. The potential at the surface is what we've been focusing on because if we know the potential at the surface, we can figure everything else out. 

[Slide 4] OK. Then we talked about these different bias regions in an N-channel transistor or P-channel transistor. We would start at flat band and if we have this ideal gate metal whose work function just happens to be right, then when we apply zero gate voltage, we have no band bending. All of the bands are flat. That's our flat band condition. No charge in the semiconductor. If we apply a negative gate potential, we pull the bands up. Positive charge accumulates at the interface. We call that accumulation. If we apply a positive gate voltage, we pull the bands down. We deplete the region near the surface and we expose the negatively charged acceptor atoms. If we apply a large enough positive bias, we pull the conduction band down close enough to the Fermi level that we get a significant number of mobile electrons. The device turns on and that's what gives us the current above threshold. 

[Slide 5] OK. We also sketched then based on those energy band diagrams what the sheet charge of the total charge in the semiconductor in coulumbs per square centimeter, what that would look like as a function of surface potential. Negative surface potential, positive charge builds up very rapidly because the number of holes in the valence band depends exponentially on how close the valence band is to the Fermi level. If we deplete the semiconductor, initially we just push the positive charge away. The depletion charge we saw vary slowly with surface potential. That's the square root. But if we bend the bands enough, then the surface potential-- then the mobile electrons will start to pile up and the mobile electron density will increase exponentially with surface potential. Notice down here, I'm being a little bit careful because I'm on a log plot here. When the charge goes to zero, log of zero is minus infinity. So we sort of cut off the charge at some arbitrary lower limit there. And we're not showing it's going to continue to go down as the surface potential goes towards zero. 

[Slide 6] OK. In Lecture 2, we discussed how under one condition, it is easy to solve the Poisson equation. The condition is that we have 1D and the condition is that we're in depletion. Then it turns out to be relatively easy to solve for the surface-- it's easy to solve for the depletion layer depth for the electric field at the surface, and for the total charge in kilohms per square centimeter in the depletion region. And they're directly related to the surface potential. So that's a derivation that's easy to do and proves to be very, very useful for us. But it only works when we're in depletion. 

[Slide 7] Now we talked in Lecture 3 about how, you know, we learned in Lecture 2 how everything depends on the surface potential. But it's the gate voltage that determines the surface potential. So in Lecture 3, we related the gate voltage to the surface potential that results. And we did that by establishing this important equation. The first term here is the voltage drop across the oxide layer. The second term is the voltage drop across the semiconductor. We add the two together and we get the voltage at the gate. And then we learned that for N depletion. There isn't much charge in the semiconductor. This term is small, so most of the gate voltage gets into the surface potential. Not all of it. This M factor is a little less than 1. But we can affect the surface potential strongly with the gate voltage. When we go above threshold, there is a lot of charge in the semiconductor. This term gets to be very big. And this term being very big means we have more and more voltage drop across the oxide. In the inversion, if we increase the gate voltage, we mostly increase the volt drop across the oxide. There is only a very small additional increase of the surface potential above 2 psi B. You know, this increase here, this is that little empirical correction with the alpha factor that I mentioned in the virtual source model. 

[Slide 8] OK. All right. We also talked about computing the threshold voltage, how much voltage do we have to apply on the gate to create an inversion layer. We began with our gate voltage, the surface potential relation. And we recognize that we have to bend the bands by this parameter 2 psi B to make the electron density at the surface equal to the hole density in the bulk. At that point, most of our charge is in the depletion region. We ignore the charge in the inversion layer at that point and we just put that together and we can compute the threshold voltage. So we get a simple expression for the threshold voltage that we can compute in terms of the doping density and thickness of the oxide and oxide capacitance, and the various terms that we can play with as we're designing transistors. Notice that we're still talking about the VT prime here. We haven't accounted for the metal-semiconductor work function difference. And that actually plays a very big role 

[Slide 9] and needs to be accounted for. OK. So these are the expressions that we developed. In depletion, we can do this calculation, you know, the charge in the semiconductor is mostly the depletion charge. We have an analytical expression for the depletion charge. So we have an equation. It turns out to be a quadratic equation that we can solve and we can determine the surface potential for a given gate voltage. So we can do that calculation in depletion, turns out to be a little bit complicated to deal with these quadratic equations. So we frequently use an even more approximate treatment in depletion. And that approximate treatment is to think about this gate insulator and semiconductor as being two capacitors in series. The semiconductor capacitance is just the capacitance of the depletion layer epsilon over the width of the depletion layer. We can simply do circuit analysis, voltage division, two capacitors in series. We're assuming that this nonlinear capacitor is just a constant capacitor at its average value. Then we can easily find that the surface potential is some fraction of the gate voltage and the fraction is determined by this parameter M which involves the ratio of these two capacitors. So that M term is something that we saw comes up over and over again. It's especially important in determining the subthreshold slope. 

[Slide 10] Well in lecture 2.4, we went back and we said, "But wait a minute. A real metal would have a metal-semiconductor work function difference. A real device might have some charge at the oxide silicon interface." And we discovered that, OK, it's easy to fix this expression up. We simply add the actual flatband voltage. It's not zero volts. It's some finite value. We simply add that finite value. We can compute the metal-semiconductor work function difference. We can compute the additional volt drop across the oxide due to that fixed charge at the oxide silicon interface. And it just shifts the curve. So it's easy to account for those non-idealities in a real device. 

[Slide 11] OK, Lectures 2.5 and Lectures 2.6. We really dove in and tried to understand how does this mobile charge, the charge that carries the current in a MOSFET, how does that vary with surface potential and with gate voltage. And the first thing we learned is that in subthreshold, it varies exponentially with surface potential. In above threshold, it varies exponentially with surface potential. There's a factor of two there in the bulk case, that factor of two isn't there in the extremely thin SOI case. The reason it's missing in the second case is because the confining potential is determined by the thickness of the silicon. In the bulk case, the confining potential is determined by the band bending and the electric field in the silicon and that ends up bringing in that factor of two. 

[Slide 12] But the important point is the mobile charge varies exponentially with surface potential, both below and above threshold. OK. So we also want to know how the mobile charge varies with gate voltage. So when we plot the mobile charge versus gate voltage, we have little charge until we exceed the threshold voltage and then the charge tends to increase linearly with gate voltage. And we did that calculation. It took a little bit of work. The bottomline was that in subthreshold, there is some mobile charge there and it's big enough to worry about. It gives us the leakage current of a MOSFET when it is supposed to be off. And the amount of that charge varies exponentially with VG minus VT over MKT. We also saw that above threshold, the mobile charge varies linearly, not exponentially with gate voltage. And we also learned that the gate capacitance in inversion is a little bit less than the oxide capacitance. It's less because we really have an oxide capacitance in series with a semiconductor capacitance. The semiconductor capacitance is not infinite. If it were, it wouldn't be a factor. But it has some finite value. So the result is that the capacitor, the capacitance here turns out to be a little bit less enough-- significantly less to worry about, less than the oxide capacitance. 

[Slide 13] When we did ETSOI, we found basically the same things happening. There is no depletion charge because we assumed that we had an intrinsic undoped silicon layer. But the mobile electron charge increases exponentially with surface potential. The mobile hole charge increases exponentially with surface potential. 

[Slide 14] So at a high level, the same things are happening. If we look at the mobile charge versus the gate voltage for that structure, subthreshold, we find again some different pre-exponential factors. But it varies exponentially with gate voltage and subthreshold. The important point to take away is that this parameter M which determines the subthreshold swing is exactly 1 in the structure. And that's an important advantage for structures like this. Above threshold, we have a similar expression in the bulk. We might have expected the capacitance to be 2 C-OX if C-OX is the capacitance of one oxide layer because I'm assuming here in this calculation that we had a double-gate structure with a gate on the top and a gate on the bottom. It turns out to be a little less than 2 C-OX because we have the semiconductor capacitance in series with everything. 

[Slide 15] OK. In Lecture 7, we finally began to look at real structures in which we have sources and drains right around the channel. We have two-dimensional fields and we asked ourselves what effect the two-dimensional electrostatics have. So two-dimensional electrostatics are responsible for some of the non-idealities that we see in transistors. So this translation of the ID-VGS characteristic with gate-- with drain voltage is a non-ideal effect. This is what we have been calling DIBL. That's a 2D electrostatic effect. That leads to a drain voltage dependent threshold voltage. Now if we go to short channel effects, short channels, these 2D effects can become very strong. The DIBL increases. The subthresholds swing might increase too and that's not a good thing. If we go to really short channels or if just haven't designed a transistor very well, we can get some very severe leakage currents. Now we're finding that the drain current is relatively insensitive to the gate voltage and the device is very hard to turn off. We say that device is punch through. So 2D electrostatics increases DIBL. And that happens when we shrink the channel length. It also happens if increase the drain voltage. The subthreshold swing might also increase at short channel lengths or at high-drain voltages. And if we have punchthrough, then we know we're dealing 

[Slide 16] with basically catastrophic 2D effects. So we spent some time in this lecture in trying to understand what the solutions to this 2D Poisson equation look like without actually solving that 2D equation. So we look at different ways. We thought about an effective doping approach. We talked about a barrier lowering picture. We talked about how the electrodes can provide geometric screening. These were all ways to understand the solutions to the 2D Poisson equation without actually doing the numerical solution. But they give us insight into what those solutions would look like. There is another useful way to analyze this that we didn't discuss, but which I would encourage you to have to look at in the lecture notes. 

[Slide 17] OK. So this concept of screening length is a very important thing and the idea here is that the electrodes or the undepleted silicon which forms a conducting layer that's like metallic can be used to image the charge on the drain, so the electric field lines penetrate on these electrodes rather than reaching through to the source where they might increase DIBL or even cause punchthrough. So if we design transistors appropriately, we want to design transistors to have short screening lengths. This is the reason that the industry is moving to structures like the FinFET. So in the FinFET, we have a vertical fin, that's our channel. And the gate is wrapped around both sides, so it's like a double-gate structure. It provides much better geometric screening. And it makes it very much harder for the field lines to get through and affect the barrier between the source and the channel. 

[Slide 18] So we ended up by saying that, you know, what we're after is an electrostatically well-designed MOSFET or a well-tempered MOSFET. It's one in which at the virtual source which is the top of this energy barrier. An equation like 1D MOS electrostatics still applies. If we carefully designed the MOSFET, that will happen. It's just we will have some DIBL so that the threshold voltage will be weakly dependent on the drain voltage. There is a region near the beginning of the channel which is under the strong control of the gate. Then we have a good transistor weakly controlled by the drain. Now if we increase the voltage on the drain, we want-- the energy band diagram will drop down because of the increased voltage. But if we have a well-designed transistor, not much will happen near the source end of the channel. That's the goal of our 2D electrostatic design producing a well-tempered MOSFET. 

[Slide 19] In the last lecture, we revisited this virtual source model. We used our improved understanding of mobile charge in subthreshold and above threshold to develop a model now that covers both subthreshold and above threshold in one smooth continuous model. And we have really succeeded in producing a pretty good model that describes nanotransistors quite accurately with only 10 device-specific parameters. 

[Slide 20] OK. We spent a little bit of time in that lecture discussing why subthreshold swing was so important, why it always has to be greater than 60 millivolts per decade, and why that is such an issue in-- prevents us from lowering the power supply and therefore lowering the power dissipation the way we would like to be able to do that in modern transistors. The holy grail of device design right now is can we find some new physics that will give us a subthreshold swing less than 60 millivolts per decade. If we can, we can lower the power supply, lower the power dissipation and that is something 

[Slide 21] that would be very advantageous. All right. So Unit 2 was all about electrostatics. If you're comfortable with these concepts, then we're ready to move on into Unit 3. Unit 3 will focus on transport. The Unit 4-- Units 3 and 4 are both on transport. But we will begin in Unit 3 with ballistic transport assuming electrons just propagate across the channel without encountering anything that impedes their motion, no scattering at all. That will be the subject of Unit 3. We'll combine our understanding of electrostatics with transport and we'll develop a model of the ballistic nanotransistor. So make sure you're comfortable with the homework assignments and the quizzes and the exam in Unit 2 and then you'll be ready to proceed on with me to Unit 3. I look forward to seeing you there.