nanoHUB-U Fundamentals of Nanotransistors/Lecture 2.6: Mobile Charge: ETSOI
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[Slide 1] Welcome back. We are in the middle of two lectures in this unit now in which we are talking about how the mobile charge varies as a function of surface potential and gate voltage. It's the mobile charge that we're interested in because that's the charge that carries the current from the source to the drain. In the last lecture, we talked about this topic in the context of bulk CMOS, that is a wafer that we could consider infinitely thick. In this lecture, we're going to address the same questions, but we're going to do it in the context of some structures that are more typical of the kinds of structures that people are using these days. So in this particular lecture, we'll look at a technology called extremely thin SOI. 

[Slide 2] So just by way of review from the last lecture, we're looking at this bulk MOSFET. By bulk, we meant that it was fabricated on the top surface of a silicon wafer, and the silicon wafer is thick enough that we could essentially assume that is was semi-infinite. Any band bending that occurs when we apply a gate voltage occurs very near the surface and we can assume that it-- all the band bending is gone by the time we get deep within the silicon. 

[Slide 3] Now, the structures that we're going to look at in this lecture is more like this. This is an extremely thin SOI MOSFET, this is work that was done at IBM research recently. You can see a transmission electron micrograph at the bottom. And you can see a cartoon at the top that shows us what we're looking at. So this is a MOSFET. If you look carefully, you can see a thin silicon layer that is on top of a bottom oxide. So that bottom oxide, you can see here in the cartoon or you can see down here in the structure. You can also see the thin silicon layer in the cartoon and you can see this thin silicon channel here in the electron micrograph. So the transistor itself is a thin layer of silicon, sitting on top of an insulating layer. There is a silicon wafer, that's the substrate, that's the role of the silicon wafer in this case is simply to support the active device. So we're going to be looking at this device and it should be clear that it's not infinitely thick. We can't regard it as infinitely thick. So the considerations-- Some of the assumptions that we made in the previous lecture simply don't apply to this structure. 

[Slide 4] But the questions are the same. So our questions are, what is the mobile charge versus surface potential or potential characteristic? And what is the mobile charge versus gate voltage characteristic for a structure like this? Now, we're going to simplify the structure even more than that transistor that we just saw. We're going to simplify it into a model double-gate structure, and it will be something-- the basic considerations that we develop in this lecture will apply to other structures as well. Structures like FinFETs which is basically a vertical structure where a gate is wrapped around both sides. We'll have a horizontal structure. 

[Slide 5] And our horizontal structure will look like this. So we'll have a thin silicon layer, we'll have a gate oxide on the top and the bottom, and we'll have metallic gate electrodes on the top and the bottom. We will assume that the thin silicon layer is fully depleted, there are no Dopants. So there's no depletion layer, no Dopants in the silicon layer. And we're going to assume that it's very thin, so there's no potential drop across it. We're going to be doing the same thing, we're going to be looking in the normal direction on this double-gate structure and asking ourselves what happens in that normal direction. 

[Slide 6] So if we were to plot an energy band diagram in the normal direction, we would have our thin silicon layer here, surrounded by two wide band gap insulators on the top and the bottom. So we've rotated everything in this particular picture. The Fermi level will be situated somewhere between the cut conduction and valence band. We're going to neglect band bending. We're going to assume that this layer is so thin that there is no electrostatic potential across the bottom of this extremely thin silicon layer, and that's why I'm drawing it as flat. And that's a reasonable assumption in these extremely thin layers. Now, one of the things that's important to recall is if you've had introductory quantum mechanics course, you remember doing a particle-in-a-box problem. That's one of the first problems that we treat in quantum mechanics. And the message from the particle-in-a-box treatment is that when you confine electrons, you discretize their energies. So here we have electrons confined in a box, it's not an infinite well, but it could be a pretty high potential well. So we expect quantum-confined energy levels, within that state just as we would get for any quantum mechanical particle. So we're going to expect a series of discrete energy levels for the transistors. And that they now-- the electrons in the conduction band can't have any energy above the bottom of the conduction band. There's a discrete subband. And that's epsilon sub 1 is the confinement energy, that's how far an energy above the bottom of the subband, above the bottom of the conduction band, the first subband is located. That's the lowest energy that an electron can have. Okay.  And then there's a second one for n equals 2 and there might be higher ones for n equals 3 or whatever. There's a set for holes also. The holes are quantum confined and the holes have a different effective of mass, so their energy levels would be a little bit different. So we have these quantum-confined electrons now in this extremely thin silicon layer. You can notice that the band gap has effectively increased because the holes can't get any higher in energy than this first subband. The electrons can't get any lower in energy than the first subband in the conduction band, so the band gap is effectively widened a little bit. 

[Slide 7] All right. Now, we're going to be interested in electrons in the conduction band and electrons in the valence band. And these are the relations we will use. We're not going to develop them here. I'll simply state them. You may have seen them before, but even if you haven't, they're reasonable. The electron density now is going to be per square centimeter. It's this sheet electron density inside this well. There's a constant effect of density of states in 2D. That is related to some material parameters like effective mass in the conduction band. And then there's a Fermi-Dirac integral when I do this integration over the density of states properly. And the argument of the Fermi-Dirac integral tells me that the electron density depends not on where the Fermi level is with respect to the bottom of the conduction band as it does in the bulk, but with respect to the lowest energy that they-- electrons can reside in which is epsilon 1 above the bottom of the conduction band. Okay.  Now, we are going to assume Boltzmann statistics just to make life simple. And then we don't have to deal with Fermi-Dirac statistics. It works reasonably well, but if we get high carrier densities, we'll worry about it quantitatively a little bit. But when I assume that the Fermi level doesn't get too close to the bottom of the subbands, then I can assume non-degenerate or Boltzmann statistics. Fermi-Diract integrals reduce to exponentials. And this is the relation that I'm going to use, very similar to the relation that we used in the bulk, but now this is a sheet electron density, a density per square meter or per square centimeter. 

[Slide 8] Now you might ask, why didn't we talk about these effects in the bulk, because we do have a potential well in the bulk when we apply a gate voltage and bend the bands down, we create a potential well for electrons at the oxide-silicon interface. You know, it's a different shape potential well. The shape of it depends on the strength of the electric field there, so it is a gate-voltage-dependent quantum well. We expect quantum confined states there and indeed they do occur. And, in fact, in modern MOS technology, people account for this, it affects things like the semiconductor capacitance that we talked about in the previous lecture. In order to quantitatively compute the semiconductor capacitance correctly, we need to account for quantum confinement in bulk MOS structures as well. Okay.  Now, an important difference is that in the bulk, the confining well is due to the potential, due to the gate voltage that we apply. In the extremely thin SOI structures that we're talking about, the confining potential is fixed, it's just the thickness of the silicon layer. Actually that makes life simpler because we can use simple particle-in-a-box expressions to deduce the energy levels. 

[Slide 9] Now, just as we did in the bulk, we're going to ask what happens when there is a potential applied, you know, and that will be applied through a gate, and the potential in the silicon changes. So if we start out with the potential 0, we may have aligned things with work functions such that the Fermi level is in the middle of the band, maybe we've ideally aligned it so that we have an equal number of electrons and holes and the system is neutral. If we apply a positive potential to the gate, we'll induce a positive potential in the silicon that will pull everything down, we'll get more electrons in the conduction band. If we apply a negative voltage to the gate, we'll get a negative surface potential, we'll pull everything up, and we'll get holes in the silicon layer. 

[Slide 10] So it's very much the same. Now, and we can develop a relation between potential and carrier density just as we did for the bulk. This is our basic relation between Fermi level and the energy levels of the states that the electrons can reside in. The bottom of the conduction band is raised or lowered depending on the value of the surface potential. So we can insert that expression into our expression for electron density, and we end up concluding that the electron density is some fixed parameters times e to the q potential over kT, very similar to the bulk. Those fixed parameters are just a value of the sheet electron density when the surface-- when the potential of the silicon is 0. So that's what I mean by nS0. And when I'm saying nS here, it means sheet carrier density per unit area. Same thing for holes. And I'm assuming now that just one of these subbands is occupied. If the Fermi level were higher in the conduction band, maybe two of them would be occupied and I would have to do this for both of them and add the results up. But the to keep things simple and just to illustrate the basic principles, we'll just assume that one is occupied. 

[Slide 11] Now, if we want to know what is the charge density in this silicon layer, well, it's just positive charge minus negative charge. There are no Dopants in this layer by assumptions so there are no ionized acceptors or donors to worry about. We have a very simple relation for the charge, positive and negative. If I'm interested just in the charge due to electrons, I just take the electron charge, so that's minus q. And our expression for electron density was its value at 0 potential times that exponential factor. And, again, just as in the bulk, this is a valid above threshold as well as below threshold. The mobile charge density varies exponentially with potential. 

[Slide 12] So if we do a plot, our plot would look something like this. This is the charge in the semiconductor versus potential in the semiconductor. If we apply a large positive voltage, most of the charge is negative, I'm plotting magnitude of charge here. So it just increases exponentially, it increases exponentially as q potential over kT. Remember in the bulk, it was q potential over 2kT. That 2 comes because of the fact that the-- confining potential in the bulk depends on the surface potential itself because the electric field is changing. In this case, the confining potential is just the thickness of the silicon. If I apply a negative potential, holes pile up and I get a positive charge. Remember, this is a log plot so I can't go down to 0. Log of 0 is minus infinity so I just cut it off at some finite value. 

[Slide 13] If we compare that to the bulk, then the bulk expression would look like this. Now, I'm being a little more careful down here, you know, the charge can't go to 0 because log of 0 is minus infinity. So we started some finite charge value, we saw that the charge increases, the depletion charge has a square root of potential. But there is no depletion charge here because we've-- we're dealing with an undoped thin silicon layer. And here's the e to qv over 2kT. In the extremely thin SOI structure, we have an e to the qv over 1kT. 

[Slide 14] So qualitatively, we see similar things, but there's no depletion charge. Now, the next step is to do exactly what we did in the bulk, and that is to relate the surface potential to the gate voltage that produced it. All right. So let's see how we go about doing that. So let's look at the electric field in the oxide, right at this interface. We can use this Gauss's Law again, the normal displacement field is minus the charge in the semiconductor. We have to be a little bit careful because we have a top gate and a bottom gate. The negative charge in this silicon layer, half of it is going to image on the top gate and half of it is going to image on the bottom gate. So when I apply Gauss's Law here, I should only make use of half of the charge, the half that is imaged on the top gate. Same thing will happen on the bottom. Okay.  Now, just as before, we want to know what is the volt drop across the oxide. It's the electric field in the oxide times the thickness of the oxide. This expression allows us to solve for the electric field, and then we get a simple relation. The volt drop is minus the charge in the silicon divided by now 2Cox. The 2 came from this division of the charge between the top and the bottom gates. To get the gate voltage, I just add the potential in the silicon to the potential drop across the oxide layer. That gives me the gate voltage, so I just add the two up and I get this expression which looks very similar to what we got in the bulk, except for this factor of 2 downstairs, right? And that's just because of the symmetry in the structure and the fact that we have two gates so that you could think of it, the capacitance is double D instead of-- when I write Cox, I mean epsilon of the oxide divided by the thickness of the oxide, but I have two gates now, so I have twice the capacitance. So if I look at this in subthreshold, here's our relation, in subthreshold the charge is negligible. So this first term is negligible. And that means that if I have negligible charge there, the gate voltage is equal to the surface potential. So when I have changed the gate voltage, I change those surface potential by exactly the same amount. That is a little bit different than we had in the bulk. Remember in the bulk, some fraction of the gate voltage got in and changed the surface potential. In this case, the quantity m, which determines that fraction, is 1. So all of the gate voltage gets in and modifies the surface potential. That is a significant difference and one that is actually very advantageous for this structure. 

[Slide 15] So here's a summary of what we've deduced, we can write the mobile charge in the silicon as a function of surface potential with is exponential relation. And because the gate voltage is equal to the surface potential in subthreshold, we can get the same kind of relation for the gate voltage dependence and it looks exponential as well. So the key point is that the gate voltage is equal to the surface potential, this factor m that we had in the bulk is 1 in this case. All right. Now, we'll do a little more algebra and this is discussed in the notes that are available to you. I'm just going to give you the result here. If I define some terms here, let me define the threshold voltage and let me define the threshold voltage this way, kT over q log effective density of states divided by the value of this electron density when the surface potential is 0. Now, if you ask what that means, what that really means is that I'm assuming that threshold occurs when the bands have been pulled down so that the Fermi level is right at the bottom of the first subband. That seems like a reasonable place, that's when I'm going to begin to get lots of electrons. Now, I can then solve this equation for nS0 and I can eliminate that from the top equation here, and I can end up with this equation. So this equation now is nice because it looks similar to our result for the bulk. We now see that the mobile charge in subthreshold goes exponentially with gate voltage minus threshold voltage, divided now by 1kT, not by mkT, that's the only difference. And when I collect up the constants out front, I'm going to find a kT over q and I'm also going to find something that has the units of capacitance. That's what people call the quantum capacitance and I'll return to that in a minute and we'll talk about what that is. But it-- When you collect up the terms after doing this algebra, you end up with q squared times the density of states, right? And that has the units of capacitance. 

[Slide 16] All right. so here's where we are. We've been looking at this gate volt, at this mobile charge versus gate voltage relation. In the subthreshold regime, we found that it goes exponentially with VG minus VT over 1kT. So just as it did in the bulk, the same conclusion there. If we compare that to the bulk case, we can see that the expressions are very similar. The pre-exponential factor is a little bit different. But in both cases we have an exponential dependence on gate voltage, that's the important takeaway message to be sure that you remember. And in the extremely thin fully depleted SOI case, this parameter m is exactly 1. That's another thing you want to try to remember. 

[Slide 17] Okay. Now we should also look above threshold, and here I'm just going to state the result. Again, you can refer to the notes for a little more discussion, but you can almost guess that it is going to be-- go linearly. That mobile charge above threshold will go linearly as V gate minus V threshold. There will be a capacitance out front. You might expect that capacitance to be twice Cox because I have a gate capacitor on the top and I have a gate capacitor on the bottom. Actually, it's a little bit less than that. And, again, it's a little bit less than that because we have a semiconductor capacitance in series with those two capacitors, just like we did before. So if I look at-- If I think about this, I think about this as I have two gate capacitors in series, in between them, I have a semiconductor capacitance, and I biased myself in strong inversion, so I'll write this as the gate capacitance in inversion. Now, the thing that's a little bit different here is that you have to remember, I only have one semiconductor capacitance and I am sharing that between the top and the bottom equally. So there's no factor of 2 down here. The factor of 2 here is because I have a top gate and I have a bottom gate. 

[Slide 18] All right. Now, just let me go back up and just talk briefly about what this quantum capacitance is that popped out of our algebra. And it's easiest to talk about it at 0 kelvin. So if I have a situation like this, where I have a lot of electrons in the conduction band and I am at 0 kelvin and I want to know how many electrons, I multiply the density of States for these two dimensional electrons, that's the number of states per unit energy that are occupied, and I multiply them by the range of energies that are occupied. And the range is just a number of states that are below the Fermi level. So it's EF minus EC minus epsilon 1. Remember that the conduction band now is just going to drop as I apply a positive gate potential, so I can write my conduction band this way, I can use that in the first expression, and I can relate the electron density in this quantum, well, at t equals 0 kelvin to the potential in the semiconductor. Okay.  Now I can say, what is the semiconductor capacitance? By definition, the semiconductor capacitance is always the derivative of charge with respect to potential. There's a minus sign there because the charge is negative and I need to get a positive capacitance. I just do this differentiation. And what you find is-- in this case, the semiconductor capacitance is q squared times the two-dimensional density of states. And that's what we defined earlier. That's what people call the quantum capacitance. It's a name for the semiconductor capacitance in this particular case. In more complex structures, the semiconductor capacitance can be a little bit more involved. But that's the basic message. So you can-- we can go back to our capacitance in inversion. It's a series combination of a top gate capacitor, a semiconductor capacitance, and a bottom gate capacitor. So when I do that series capacitance, you'll see that it is always less than twice the capacitance of the Cox on the top and Cox on the bottom. And it's less because of that semiconductor capacitance in series. And that semiconductor capacitance, that quantum capacitance is a semiconductor capacitance. And you can already anticipate if you were going to build a MOSFET on a low effective mass, low density of states material, like a III-V, then, you would have a lower quantum capacitance. A lower quantum capacitance is going to lower the overall capacitance and that would hurt you because normally, we want a high capacitance to get high charge. So we can get that kind of qualitative insight on how effective mass affects semiconductor capacitance from this expression. 

[Slide 19] All right. So just to summarize, here is where we stand. We have derived the gate voltage, the mobile charge versus gate voltage expressions below threshold and above threshold for this ETSOI structure. And we have, in the previous lecture, done exactly the same thing for the bulk structure. And you can see that they're very similar. So in both cases, the subthreshold charge varies exponentially as e to the gate voltage minus threshold voltage over 1kT for the ETSOI, over mkT for the bulk. And we hope that m is close to 1. In the ETSOI structure, the double-gate ETSOI structure, the one that has a gate on the top and the gate in the bottom, which is sort of like a thin FinFET, where the thing is just turned vertically. In a double gate structure, the gate capacitance in inversion is roughly twice Cox because of those two gates, actually, less because of the quantum capacitance. And then the single gate structure, we only have 1 Cox. A little bit less because of the semiconductor capacitance. 

[Slide 20] Now, I want to make an aside that we will come back to this in a later lecture and talk in more detail where we will show that the subthreshold swing is 2.3m times kT. And we'll explain why you want a low subthreshold swing as low as possible, which means you want m as small as possible. M equals 1 for this fully depleted ETOI-- ETSOI structure, and that-- and actually a very significant advantage of structures like that to get us low subthreshold swing. 

[Slide 21] Okay.  We can wrap up and summarize. In the last two lectures, we've covered a lot of ground, but there are only a few key takeaways. So we've considered 1D MOS electrostatics in the normal direction. We now understand how the mobile charge varies with gate voltage both below threshold, where it goes exponentially, and above threshold where it goes linearly. And we've seen that the same basic considerations apply to these two much different structures. There's just some little differences in the formulas that we derived. Now, in our next lecture, we're going to need to address 2D electrostatics. We have been talking about the problem of electrostatics in the direction normal to the channel, ignoring the fact that we've got a source and drain here than there are electric fields due to the depletion regions on those structures. Okay.  But in modern transistors, this channel length is very short. And we cannot ignore the presence of the source and the drain. We have much more complicated two-dimensional potential profiles, and that's the very important topic of 2D MOS electrostatics and that will be the subject of the next lecture. Thank you.