ECE 695R: System-on-Chip Design
Course overview Offering: o1a Section: Default
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Unit 1: Introduction and Background
Lectures
- L1.1: SoCs - What & Why?
- L1.2: Course Overview
- L1.3: Taxonomy of ICs
- L1.4: Levels of Design Abstraction
- L1.5: Overview of SoC Design Flow
- L1.6: SoC Design – Behavioral Synthesis
- L1.7: SoC Design – On-Chip Communication Architecture
- L1.8: SoC Design – Modeling and Co-Simulation
Unit 2: HW/SW Partitioning
Lectures
- L2.1: Objective of HW/SW Partitioning
- L2.2: Application-Specific HW Efficiency
- L2.3: Target Architectures and HW Accelerator Design
- L2.4: HW/SW Interfacing Basics
- 2.5: Avalon System: Memory-Mapped Interface I
- L2.6: Avalon System: Memory-Mapped Interface II
- L2.7: Avalon System: Pipelined and Burst Transfers
- L2.8: Avalon System: Interconnect Fabric
- L2.9: HW/SW Co-Synthesis
- L2.10: HW/SW Co-Synthesis: An ILP Formulation I
- L2.11: HW/SW Co-Synthesis: An ILP Formulation II
- L2.12: HW/SW Co-Synthesis: An Example
- L2.13: HW/SW Co-Synthesis: Automatic Partitioning
- L2.14: Application Specific Instruction Processors (ASIPs)
- L2.15: ASIP: Approaches to Design
- L2.16: NiosII: Custom Instruction Design I 00:12 ASIP Design using NiosII: Outline
- L2.17: NiosII: Custom Instruction Design II
- L2.18: NiosII: Custom Instructions in Software
- L2.19: Automatic Custom Instruction Generation
- L2.20: Automatic Custom Instruction Generation – Local General
- L2.21: Automatic Custom Instruction Generation – Pruning
- L2.22: Automatic Custom Instruction Generation - Re-use
- L2.23: Automatic Custom Instruction Generation – Tensilica XPRES
- L2.24: Example: Embedded Web Server
- L2.25: Example: MOSES (Mobile Security Processing System)
- L2.26: Example: MOSES Hardware Architecture
Unit 3: Behavioral Synthesis
Lectures
- L3.1: Overview
- L3.2: Major Steps - Scheduling and Allocation
- L3.3: Major Steps – Binding/Assignment
- L3.4: Scheduling
- L3.5: Heuristic Scheduling – ASAP and ALAP
- L3.6: List Scheduling
- L3.7: Force-directed Scheduling I
- L3.8: Force-directed Scheduling II
- L3.9: Path-based Scheduling I
- L3.10: Path-based Scheduling II
- L3.11: Detailed Timing Constraints
- L3.12: Resource Sharing
- L3.13: Resource Sharing - Examples
- L3.14: Resource Sharing - Algorithms
- L3.15: Behavioral Transformations
- L3.16: Advanced Pipelining
- L3.17: Scheduling with Speculative Execution
- L3.18: SIMD Units
- L3.19: Summary
Unit 4: On-chip Communication Architecture
Lectures
- L4.1: Overview
- L4.2: On-chip Buses
- L4.3: AMBA 2.0 – AHB & APB
- L4.4: AMBA 3.0/4.0 – AXI
- L4.5: Customization
- L4.6: Customization – Adaptive I
- L4.7: Customization – Adaptive II
- L4.8: Arbitration Techniques – Priority-Based and TDMA
- L4.9: Arbitration Techniques – LOTTERYBUS
- L4.10: Arbitration Techniques – SAMBA-Bus
- L4.11: Arbitration Techniques – CDMA-Bus and Summary
Unit 5: Network on Chip
Lectures
- L5.1: Why NoC's?
- L5.2: Topology I
- L5.3: Topology II
- L5.4: Routing Algorithm I
- 5.5: Routing Algorithm II
- L5.6: Switching Strategy I
- L5.7: Switching Strategy II
- L5.8: Flow Control Mechanism