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Contributors: View

Pallav Gupta

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Contributions 3
Affiliation VIllanova University
Web Site http://pandim.ece.villanova.edu

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  1. Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2

    This resource has a 7.3 Ranking

    Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›

    Usage Stats
    Last 12 Months: updated 01 May, 2008
    Users: 14
    Reviews & Citations
    Google/IEEE
    Avg. Review: 0.0 out of 5 stars
    Citations: 0

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    08 Jan. 2008 | Downloads | Contributor(s): James Donald, Pallav Gupta

    Reed-Muller Reversible Logic Synthesis tool (a.k.a. RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS features reversible logic synthesis with SWAP, Fredkin, and Peres gates. This work was done under the …

  2. RMRLS 0.2

    This resource has a 7.3 Ranking

    Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›

    Usage Stats
    Last 12 Months: updated 01 May, 2008
    Users: 14
    Reviews & Citations
    Google/IEEE
    Avg. Review: 0.0 out of 5 stars
    Citations: 0

    0 reviews (Review this)

    0 citations

    08 Jan. 2008 | Downloads | Contributor(s): James Donald, Pallav Gupta

    Reed-Muller Reversible Logic Synthesis tool (aka RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS a.k.a. RELOS features reversible logic synthesis with SWAP, Fredkin, and Peres gates.This work was done under …

  3. ThrEshold Logic Synthesizer (TELS) and Majority Logic Synthezier (MALS)

    This resource has a 8.4 Ranking

    Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›

    Usage Stats
    Last 12 Months: updated 01 May, 2008
    Users: 31
    Reviews & Citations
    Google/IEEE
    Avg. Review: 0.0 out of 5 stars
    Citations: 0

    0 reviews (Review this)

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    15 Oct. 2007 | Downloads | Contributor(s): Pallav Gupta

    TELS and MALS are threshold and majority/minority logic synthesis tools that were developed by Rui Zhang and Pallav Gupta under the supervision of Prof. Niraj K. Jha of Princeton University. Dr. Lin Zhong, of Rice University, was also a contributor. Both of these tools have been integrated into …

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Results 1 - 3 of 3