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David J. Frank
| Contributions | 1 |
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| Affiliation | IBM Research Division, Thomas J. Watson Research Center |
| Biography | Dr. Frank received his B.S. from the California Institute of Technology, Pasadena, CA in 1977 and a Ph.D. in physics from Harvard University, Cambridge, MA in 1983. Since graduation he has been employed at the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is a Research Staff Member. His studies have included non-equilibrium superconductivity, III-V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, analysis of CMOS scaling issues such as power consumption, discrete dopant effects and short-channel effects associated with high-k gate insulators, exploring various nanotechnologies, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low power circuit design. Dr. Frank is an IEEE Fellow and has served as chairman of the Si Nanoelectronics Workshop and is an associate editor of IEEE Transactions on Nanotechnology. He has authored or co-authored 100 technical publications and holds 10 U.S. Patents. |
Contributions
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The Limits of CMOS Scaling from a Power-Constrained Technology Optimization Perspective
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17 Oct. 2006 | Online Presentations | Contributor(s): David J. Frank
As CMOS scaling progresses, it is becoming very clear that power dissipation plays a dominant role in limiting how far scaling can go. This talk will briefly describe the various physical effects that arise at the limits of scaling, and will then turn to an analysis of scaling in the presence of …