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Contributors: View

Anisur Rahman

Contributor picture

Contributions 4
Affiliation Purdue University, West Lafayette
Biography Anisur Rahman received his BSc in Electrical Engineering in 1997 from Bangladesh University of Engineering and Technology (BUET), Dhaka, Bangladesh. After that, he joined the Department of EEE at BUET and worked for two years as a lecturer. From fall 1999, he pursued a direct PhD program in Electrical Engineering at Purdue University, West Lafayette, IN, which he finished in 2005. Since September 2005, he has been working in the Front End Quality and Reliability group at Intel Corp., Hillsboro, OR.

Contributions

  1. Bandstructure Lab

    This resource has a 10.0 Ranking

    Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›

    Usage Stats
    Last 12 Months: Updated 16 May, 2008 more ›
    Users: 877
    Jobs: 6491
    Avg. exec. time: 8 mins
    Reviews & Citations
    Google/IEEE: updated 05 Feb, 2008
    Avg. Review: 5.0 out of 5 stars
    Citations: 3

    3 reviews (Review this)

    3 citations

    19 May. 2006 | Tools | Contributor(s): Mathieu Luisier, Raseong Kim, Neophytos Neophytou, Michael McLennan, Jing Wang, Anisur Rahman, Gerhard Klimeck, Mark Lundstrom

    Simulate electronic band structure for a variety of bulk materials and device geometries such as quantum wells and nanowires.

  2. Exploring New Channel Materials for Nanoscale CMOS

    This resource has a 9.1 Ranking

    Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›

    Usage Stats
    Last 12 Months: updated 01 May, 2008
    Users: 180
    Reviews & Citations
    Google/IEEE
    Avg. Review: 4.5 out of 5 stars
    Citations: 0

    2 reviews (Review this)

    0 citations

    21 May. 2006 | Publications | Contributor(s): Anisur Rahman

    The improved transport properties of new channel materials, such as Ge and III-V semiconductors, along with new device designs, such as dual gate, tri gate or FinFETs, are expected to enhance the performance of nanoscale CMOS devices. Novel process techniques, such as ALD, high-k dielectrics, and …

  3. FETToy

    This resource has a 9.5 Ranking

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    Usage Stats
    Last 12 Months: Updated 16 May, 2008 more ›
    Users: 482
    Jobs: 5907
    Avg. exec. time: 5 secs
    Reviews & Citations
    Google/IEEE: updated 28 Apr, 2008
    Avg. Review: 5.0 out of 5 stars
    Citations: 11

    7 reviews (Review this)

    11 citations

    14 Feb. 2006 | Tools | Contributor(s): Anisur Rahman, Jing Wang, Jing Guo, Sayed Hasan, Yang Liu, Akira Matsudaira, Shaikh S. Ahmed, Supriyo Datta, Mark Lundstrom

    Toy model to simulate I-V characteristics of nanoscale double gate MOSFETs

  4. Theory of Ballistic Nanotransistors

    This resource has a 5.5 Ranking

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    Usage Stats
    Last 12 Months: updated 01 May, 2008
    Users: 2
    Reviews & Citations
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    Avg. Review: 0.0 out of 5 stars
    Citations: 0

    0 reviews (Review this)

    0 citations

    27 Nov. 2002 | Publications | Contributor(s): Anisur Rahman, Jing Guo, Supriyo Datta, Mark Lundstrom

    Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional electrostatic effects are small, (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to …