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Kaushik Roy
| Contributions | 3 (detailed usage) |
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| Affiliation | Purdue University, West Lafayette |
| Web Site | http://dynamo.ecn.purdue.edu/~kaushik/ |
| Biography | Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the Electrical and Computer Engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the Electrical and Computer Engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor and holds the Roscoe H. George Professor of Electrical and Computer Engineering. His research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. Dr. Roy has published more than 300 papers in refereed journals and conferences, holds 8 patents, and is a co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, and 2004 IEEE International Conference on Computer Design. Dr. Roy is currently a Purdue University Faculty Scholar. He is the Chief Technical Advisor of Zenasis Inc. and Research Visionary Board Member of Motorola Labs (2002). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, and IEEE Transactions on VLSI Systems. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002). Dr. Roy is a fellow of IEEE. |
Contributions
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Design in the Nanometer Regime: Process Variation
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Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›
Usage Stats Last 12 Months: updated 01 Jun, 2008 Users: 208 Reviews & Citations Google/IEEE Avg. Review: Citations: 0
208 users
29 Nov. 2006 | Online Presentations | Contributor(s): Kaushik Roy
Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems — severe short channel effects, exponential increase in …
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Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance
- This resource has a 10.0 Ranking
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Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›
Usage Stats Last 12 Months: updated 01 Jun, 2008 Users: 184 Reviews & Citations Google/IEEE Avg. Review: Citations: 0
184 users
28 Nov. 2006 | Online Presentations | Contributor(s): Kaushik Roy
Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems: severe short channel effects, exponential increase in …
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PETE: Purdue Exploratory Technology Evaluator
- This resource has a 8.7 Ranking
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Ranking is calculated from a formula comprised of user reviews and usage statistics. Learn more ›
Usage Stats Overall Period: Updated 03 Jul, 2008 Users: 106 Jobs: 3285 Avg. exec. time: 3 mins Reviews & Citations Google/IEEE Avg. Review: Citations: 0
106 users, detailed statistics
27 Jun. 2007 | Tools | Contributor(s): Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, Kaushik Roy
Using PETE one can evaluate any MOSFET like devices or any New Devices in terms of performance on Benchmark circuits. The input to the tool can be in terms of typical MOSFET parameters or in terms of I-V and C-V tables. The Benchmark circuits include minim