Synopsys digital design

By Harish Balan¹; Ali Shamsapour¹; Jesse Flores¹; Steven Clark²; Juan Carlos Verduzco Gastelum²; Alejandro Strachan²

1. Synopsys, Inc. 2. Purdue University

Digital design using Synopsys EDA

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Version 1.2 - published on 21 Apr 2024

doi:10.21981/JB3P-5976 cite this

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Usage

World usage

Location of all "Synopsys digital design" Users Since Its Posting

• Monthly
• Yearly
• Cumulative

Cumulative Simulation Users

7

7 7

Simulation Runs

130 Apr 2024

103 130

Overview

	Average	Total
Wall Clock Time	2.79 hours	9.41 days
CPU time	10.88 seconds	14.69 minutes
Interaction Time	20.98 minutes	1.18 days